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mb/google/puff/var/*: Set LAN device type back to pci 

This mostly reverts commit 6c705e766f ("mb/google/puff/var/*: Set
LAN/WLAN device type to generic"). Setting the LAN device type to
generic broke programming the LAN MAC address, so set it back to pci.

TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed
correctly.

Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Matt DeVillier 2023-11-19 16:12:56 -06:00 committed by Felix Held
parent c08461dfd4
commit f03b8fc370
10 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/puff/variants/ambassador/overridetree.cb
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@ -396,7 +396,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/duffy/overridetree.cb
View File

@ -455,7 +455,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/faffy/overridetree.cb
View File

@ -429,7 +429,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/genesis/overridetree.cb
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@ -426,7 +426,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
end
device pci 1c.7 on # PCI Root Port 8 (WLAN)

2
src/mainboard/google/puff/variants/kaisa/overridetree.cb
View File

@ -455,7 +455,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
View File

@ -428,7 +428,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
end
device pci 1c.7 on # PCI Root Port 8 (WLAN)

2
src/mainboard/google/puff/variants/noibat/overridetree.cb
View File

@ -366,7 +366,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/puff/overridetree.cb
View File

@ -390,7 +390,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/scout/overridetree.cb
View File

@ -406,7 +406,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
end
device pci 1c.7 on # PCI Root Port 8 (WLAN)

2
src/mainboard/google/puff/variants/wyvern/overridetree.cb
View File

@ -391,7 +391,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device generic 0 on end
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC