mb/google/puff/var/*: Set LAN device type back to pci

This mostly reverts commit 6c705e766f ("mb/google/puff/var/*: Set
LAN/WLAN device type to generic"). Setting the LAN device type to
generic broke programming the LAN MAC address, so set it back to pci.

TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed
correctly.

Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>

src/mainboard/google/puff/variants/ambassador/overridetree.cb

@@ -396,7 +396,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC

src/mainboard/google/puff/variants/duffy/overridetree.cb

@@ -455,7 +455,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC

src/mainboard/google/puff/variants/faffy/overridetree.cb

@@ -429,7 +429,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC

src/mainboard/google/puff/variants/genesis/overridetree.cb

@@ -426,7 +426,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 		end
 		device pci 1c.7 on # PCI Root Port 8 (WLAN)

src/mainboard/google/puff/variants/kaisa/overridetree.cb

@@ -455,7 +455,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC

src/mainboard/google/puff/variants/moonbuggy/overridetree.cb

@@ -428,7 +428,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 		end
 		device pci 1c.7 on # PCI Root Port 8 (WLAN)

src/mainboard/google/puff/variants/noibat/overridetree.cb

@@ -366,7 +366,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC

src/mainboard/google/puff/variants/puff/overridetree.cb

@@ -390,7 +390,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC

src/mainboard/google/puff/variants/scout/overridetree.cb

@@ -406,7 +406,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 		end
 		device pci 1c.7 on # PCI Root Port 8 (WLAN)

src/mainboard/google/puff/variants/wyvern/overridetree.cb

@@ -391,7 +391,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
-				device generic 0 on end
+				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC