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Fixup the 440BX northbridge.c (self-ack as this wasn't working anyway). 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2007-05-10 23:59:20 +00:00
parent d03b7d4289
commit f03e4e97ce
1 changed files with 4 additions and 7 deletions
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11
src/northbridge/intel/i440bx/northbridge.c
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@ -96,6 +96,7 @@ static void pci_domain_set_resources(device_t dev)
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
* This is all computed in kilobytes and converted to/from
@ -114,6 +115,7 @@ static void pci_domain_set_resources(device_t dev)
*/
tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)) << 13;
printk_debug("Setting RAM size to %d MB\n", tomk >> 10);
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
@ -121,17 +123,12 @@ static void pci_domain_set_resources(device_t dev)
*/
tolmk = tomk;
}
/* Write the ram configuration registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);
tolm_r = ((tolmk >> 10) << 3) | (tolm_r & 0xf);
pci_write_config16(mc_dev, 0xc4, tolm_r);
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
// ram_resource(dev, idx++, 768, tolmk - 768);
ram_resource(dev, idx++, 1024, tolmk - 1024);
}
assign_resources(&dev->link[0]);
}