mb/google/dedede/var/driblee: Configure audio setting
Update the combination audio CS42L42 and amp. MAX98360. BUG=b:195619349, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I264c680ed5638b71c912253a38c27152a9015d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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@ -177,6 +177,7 @@ config BOARD_GOOGLE_DRIBLEE
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bool "-> Driblee"
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select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
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select BASEBOARD_DEDEDE_LAPTOP
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select DRIVERS_GENERIC_MAX98357A
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config BOARD_GOOGLE_GOOEY
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bool "Gooey"
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@ -86,11 +86,36 @@ chip soc/intel/jasperlake
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device pci 15.1 off end # I2C 1
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device pci 15.2 off end # I2C 2
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device pci 15.3 off end # I2C 3
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device pci 19.0 on
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chip drivers/i2c/cs42l42
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H16)"
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register "ts_inv" = "true"
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register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
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register "ts_dbnc_fall" = "FALL_DEB_0_MS"
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register "btn_det_init_dbnce" = "100"
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register "btn_det_event_dbnce" = "10"
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register "bias_lvls[0]" = "15"
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register "bias_lvls[1]" = "8"
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register "bias_lvls[2]" = "4"
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register "bias_lvls[3]" = "1"
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register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
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register "hs_bias_sense_disable" = "true"
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device i2c 48 on end
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end
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end #I2C 4
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device pci 1e.2 off end # GSPI 0
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end # Discrete TPM
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end # chip drivers/pc80/tpm
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end # PCH eSPI
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device pci 1f.3 on
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chip drivers/generic/max98357a
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register "hid" = ""MX98360A""
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
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device generic 0 on end
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end
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end # Intel HDA
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end
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end
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