soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` config

List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.

Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/google/dedede/variants/baseboard/devicetree.cb

@@ -203,9 +203,6 @@ chip soc/intel/jasperlake
 	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
 	register "PchPmPwrCycDur" = "1"       # 1s
 
-	# Enable HECI
-	register "HeciEnabled" = "1"
-
 	# Set xHCI LFPS period sampling off time, the default is 9ms.
 	register "xhci_lfps_sampling_offtime_ms" = "9"
 

src/mainboard/intel/jasperlake_rvp/Kconfig

@@ -33,6 +33,9 @@ config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
 
 if BOARD_INTEL_JASPERLAKE_RVP_COMMON
 
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y
+
 config MAINBOARD_DIR
 	default "intel/jasperlake_rvp"
 

src/soc/intel/jasperlake/chip.h

@@ -142,10 +142,6 @@ struct soc_intel_jasperlake_config {
 	/* Gfx related */
 	uint8_t SkipExtGfxScan;
 
-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
-
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
 

src/soc/intel/jasperlake/smihandler.c

@@ -16,11 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_jasperlake_config *config;
-
-	config = config_of_soc();
-
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
 		heci_disable();
 }