google/oak: Initialize i2c bus timing register for TPM and external buck
BRANCH=none BUG=none TEST=build pass and boot to oak kernel Change-Id: Id2c3bbb70a1de54a56ee04ecda76178b1bdf1a4d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9 Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9 Original-Signed-off-by: jun.gao <jun.gao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319031 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -18,6 +18,7 @@
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#include <bootblock_common.h>
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#include <delay.h>
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#include <soc/gpio.h>
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#include <soc/i2c.h>
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#include <soc/mt6391.h>
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#include <soc/pericfg.h>
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#include <soc/pinmux.h>
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@ -78,6 +79,9 @@ void bootblock_mainboard_init(void)
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/* set nor related GPIO */
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nor_set_gpio_pinmux();
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/* Init i2c bus 2 Timing register for TPM */
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mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
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setup_chromeos_gpios();
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@ -23,6 +23,7 @@
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#include <elog.h>
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#include <gpio.h>
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#include <soc/bl31_plat_params.h>
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#include <soc/i2c.h>
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#include <soc/mt6391.h>
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#include <soc/mtcmos.h>
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#include <soc/pinmux.h>
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@ -53,6 +54,9 @@ static void register_da9212_to_bl31(void)
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},
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};
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register_bl31_param(¶m_da9212.h);
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/* Init i2c bus Timing register for da9212 */
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mtk_i2c_bus_init(param_da9212.i2c_bus);
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#endif
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}
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@ -66,6 +70,9 @@ static void register_mt6311_to_bl31(void)
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.i2c_bus = 1,
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};
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register_bl31_param(¶m_mt6311.h);
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/* Init i2c bus Timing register for mt6311 */
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mtk_i2c_bus_init(param_mt6311.i2c_bus);
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#endif
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}
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@ -119,6 +126,9 @@ static void configure_audio(void)
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mt6391_gpio_output(MT6391_KP_COL4, 1);
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mt6391_gpio_output(MT6391_KP_COL5, 1);
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/* Init i2c bus Timing register for audio codecs */
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mtk_i2c_bus_init(0);
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/* set I2S clock to 48KHz */
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mt_pll_set_aud_div(48 * KHz);
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}
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