exynos5xxx: use oscillator clock when changing ARM frequency

Switch ARM clock source when changing the APLL frequency to avoid
stability issues.

This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8
Reviewed-on: https://gerrit.chromium.org/gerrit/64838
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4442
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/cpu/samsung/exynos5250/clock_init.c

@@ -102,6 +102,9 @@ void system_clock_init(struct mem_timings *mem,
 		val = readl(&clk->div_stat_cpu1);
 	} while (0 != val);
 
+	/* switch A15 clock source to OSC clock before changing APLL */
+	clrbits_le32(&clk->src_cpu, APLL_FOUT);
+
 	/* Set APLL */
 	writel(APLL_CON1_VAL, &clk->apll_con1);
 	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
@@ -110,6 +113,9 @@ void system_clock_init(struct mem_timings *mem,
 	while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
 		;
 
+	/* now it is safe to switch to APLL */
+	setbits_le32(&clk->src_cpu, APLL_FOUT);
+
 	/* Set MPLL */
 	writel(MPLL_CON1_VAL, &clk->mpll_con1);
 	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);

src/cpu/samsung/exynos5250/setup.h

@@ -38,6 +38,8 @@ struct exynos5_phy_control;
 #define TZPC8_BASE		0x10180000
 #define TZPC9_BASE		0x10190000
 
+#define APLL_FOUT	(1 << 0)
+
 /* APLL_CON1	*/
 #define APLL_CON1_VAL	(0x00203800)
 

src/cpu/samsung/exynos5420/clock_init.c

@@ -60,6 +60,9 @@ void system_clock_init(void)
 	writel(HPM_RATIO,  &clk->clk_div_cpu1);
 	writel(CLK_DIV_CPU0_VAL, &clk->clk_div_cpu0);
 
+	/* switch A15 clock source to OSC clock before changing APLL */
+	clrbits_le32(&clk->clk_src_cpu, APLL_FOUT);
+
 	/* Set APLL */
 	writel(APLL_CON1_VAL, &clk->apll_con1);
 	val = set_pll(0xc8, 0x3, 0x1);
@@ -67,9 +70,15 @@ void system_clock_init(void)
 	while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
 		;
 
+	/* now it is safe to switch to APLL */
+	setbits_le32(&clk->clk_src_cpu, APLL_FOUT);
+
 	writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc);
 	writel(CLK_DIV_KFC_VAL, &clk->clk_div_kfc0);
 
+	/* switch A7 clock source to OSC clock before changing KPLL */
+	clrbits_le32(&clk->clk_src_kfc, KPLL_FOUT);
+
 	/* Set KPLL*/
 	writel(KPLL_CON1_VAL, &clk->kpll_con1);
 	val = set_pll(0xc8, 0x2, 0x2);
@@ -77,6 +86,9 @@ void system_clock_init(void)
 	while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
 		;
 
+	/* now it is safe to switch to KPLL */
+	setbits_le32(&clk->clk_src_kfc, KPLL_FOUT);
+
 	/* Set MPLL */
 	writel(MPLL_CON1_VAL, &clk->mpll_con1);
 	val = set_pll(0xc8, 0x3, 0x1);

src/cpu/samsung/exynos5420/setup.h

@@ -45,6 +45,9 @@ struct exynos5_phy_control;
 #define TZPC8_BASE		0x10180000
 #define TZPC9_BASE		0x10190000
 
+#define APLL_FOUT	(1 << 0)
+#define KPLL_FOUT	(1 << 0)
+
 /* APLL_CON1	*/
 #define APLL_CON1_VAL	(0x0020f300)