vc/amd/fsp/picasso: Add PCIe and DDI helpers
Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Marshall Dawson
Felix Held
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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/*
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* These definitions are used to describe PCIe bifurcation and display physical
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* connector types connected to the SOC.
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*/
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#ifndef __PI_PICASSO_PLATFORM_DESCRIPTORS_H__
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#define __PI_PICASSO_PLATFORM_DESCRIPTORS_H__
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/* Engine descriptor type */
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typedef enum {
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UNUSED_ENGINE = 0x00, // Unused descriptor
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PCIE_ENGINE = 0x01, // PCIe port
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USB_ENGINE = 0x02, // USB port
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SATA_ENGINE = 0x03, // SATA
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DP_ENGINE = 0x08, // Digital Display
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ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe)
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MAX_ENGINE // Max engine type for boundary check.
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} dxio_engine_type;
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/* PCIe link capability/speed */
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typedef enum {
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GEN_MAX = 0, // Maximum supported
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GEN1,
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GEN2,
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GEN3,
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GEN_INVALID // Max Gen for boundary check
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} dxio_link_speed_cap;
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/* SATA ChannelType initialization */
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typedef enum {
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SATA_CHANNEL_OTHER = 0, // Default Channel Type
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SATA_CHANNEL_SHORT, // Short Trace Channel Type
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SATA_CHANNEL_LONG // Long Trace Channel Type
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} dxio_sata_channel_type;
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/* CLKREQ for PCIe type descriptors */
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typedef enum {
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CLK_DISABLE = 0x00,
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CLK_REQ0,
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CLK_REQ1,
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CLK_REQ2,
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CLK_REQ3,
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CLK_REQ4,
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CLK_REQ5,
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CLK_REQ6,
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CLK_REQ7,
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CLK_REQ8,
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CLK_REQGFX = 0x0c,
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} cpm_clk_req;
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/* PCIe link ASPM initialization */
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typedef enum {
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ASPM_DISABLED = 0, // Disabled
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ASPM_L0s, // PCIe L0s link state
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ASPM_L1, // PCIe L1 link state
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ASPM_L0sL1, // PCIe L0s & L1 link state
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ASPM_MAX // Not valid value, used to verify input
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} dxio_aspm_type;
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/* DDI Aux channel */
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typedef enum {
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AUX1 = 0,
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AUX2,
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AUX3,
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AUX4,
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AUX5,
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AUX6,
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AUX_MAX // Not valid value, used to verify input
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} pcie_aux_type;
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/* DDI Hdp Index */
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typedef enum {
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HDP1 = 0,
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HDP2,
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HDP3,
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HDP4,
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HDP5,
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HDP6,
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HDP_MAX // Not valid value, used to verify input
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} pcie_hdp_type;
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/* DDI display connector type */
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typedef enum {
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DP = 0, // DP
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EDP, // eDP
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SINGLE_LINK_DVI, // Single Link DVI-D
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DUAL_LINK_DVI, // Dual Link DVI-D
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HDMI, // HDMI
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DP_TO_VGA, // DP-to-VGA
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DP_TO_LVDS, // DP-to-LVDS
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NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA
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SINGLE_LINK_DVI_I, // Single Link DVI-I
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CRT, // CRT (VGA)
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LVDS, // LVDS
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EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init
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EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init
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AUTO_DETECT, // VBIOS auto detect connector type
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UNUSED_PTYPE, // UnusedType
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MAX_CONNECTOR_TYPE // Not valid value, used to verify input
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} pcie_connector_type;
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/* DDI Descriptor: used for configuring display outputs */
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typedef struct __packed {
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uint8_t connector_type;
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uint8_t aux_index;
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uint8_t hdp_index;
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uint8_t reserved;
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} fsp_ddi_descriptor;
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/* PCIe Descriptor: used for assigning lanes, bifurcation and other settings */
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/* Since the code will always be compiled as little endian, using a bitfield struct should be
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safe here. */
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typedef struct __packed {
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uint8_t engine_type;
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uint8_t start_lane; // Start lane of the pci device
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uint8_t end_lane; // End lane of the pci device
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uint8_t gpio_group_id; // FCH reset number. 0 is global reset
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unsigned int port_present :1; // Should be TRUE if train link
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unsigned int reserved_3 :7;
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unsigned int device_number :5; // Desired root port device number
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unsigned int function_number :3; // Desired root port function number
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unsigned int link_speed_capability :2;
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unsigned int auto_spd_change :2;
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unsigned int eq_preset :4;
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unsigned int link_aspm :2;
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unsigned int link_aspm_L1_1 :1;
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unsigned int link_aspm_L1_2 :1;
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unsigned int clk_req :4;
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uint8_t link_hotplug;
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uint8_t slot_power_limit;
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unsigned int slot_power_limit_scale :2;
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unsigned int reserved_4 :6;
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unsigned int link_compliance_mode :1;
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unsigned int link_safe_mode :1;
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unsigned int sb_link :1;
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unsigned int clk_pm_support :1;
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unsigned int channel_type :3;
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unsigned int turn_off_unused_lanes :1;
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uint8_t reserved[4];
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} fsp_pcie_descriptor;
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#endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */
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