From f070253659d0e0aaeefa2a65b42cc1fa448e5829 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 22 Jul 2021 23:11:11 +0200 Subject: [PATCH] soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bit TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN APU that the McaXEnable bit is set in the CONFIG registers of all used MCAX banks. Signed-off-by: Felix Held Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/amd/common/block/cpu/mca/mcax.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c index a4b5c59b03..46c72f00a8 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax.c +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -7,6 +7,9 @@ #include #include "mca_common_defs.h" +/* The McaXEnable bit in the config registers of the available MCAX banks is already set by the + FSP, so no need to set it here again. */ + bool mca_skip_check(void) { /* On Zen-based CPUs/APUs the MCA(X) status register have a defined state even in the