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Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol 

This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1
substate for PCIe.

BRANCH=None
BUG=chrome-os-partner:42331
TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows
"L1 enabled and LTR enabled"

Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83
Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284775
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Naveen Krishna Chatradhi 2015-07-06 16:42:56 +05:30 committed by Patrick Georgi
parent 02b3243dd3
commit f077de66ff
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/intel/sklrvp/Kconfig
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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MARK_GRAPHICS_MEM_WRCOMB select MARK_GRAPHICS_MEM_WRCOMB
select MMCONF_SUPPORT select MMCONF_SUPPORT
select MONOTONIC_TIMER_MSR select MONOTONIC_TIMER_MSR
select PCIEXP_L1_SUB_STATE
select INTEL_PCH_UART_CONSOLE select INTEL_PCH_UART_CONSOLE
select SOC_INTEL_SKYLAKE select SOC_INTEL_SKYLAKE
select VBOOT_DYNAMIC_WORK_BUFFER select VBOOT_DYNAMIC_WORK_BUFFER