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google/panther: Fix thermal zone to use SIO PWM/TACH port 2 

Fan is attached to port 2 instead of 3.
(panther port of I9878063a24b0b908c74522580f776a4ce7d03d75)

BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther

Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174984
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5991
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Mohammed Habibulla 2013-10-29 11:02:30 -07:00 committed by Patrick Georgi
parent 0fccebb5d9
commit f0790e4e51
1 changed files with 10 additions and 10 deletions
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20
src/mainboard/google/panther/acpi/thermal.asl
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@ -141,12 +141,12 @@ Scope (\_TZ)
} }
Method (_ON) { Method (_ON) {
Store (0, \FLVL) Store (0, \FLVL)
Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
Method (_OFF) { Method (_OFF) {
Store (1, \FLVL) Store (1, \FLVL)
Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
} }
@ -162,12 +162,12 @@ Scope (\_TZ)
} }
Method (_ON) { Method (_ON) {
Store (1, \FLVL) Store (1, \FLVL)
Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
Method (_OFF) { Method (_OFF) {
Store (2, \FLVL) Store (2, \FLVL)
Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
} }
@ -183,12 +183,12 @@ Scope (\_TZ)
} }
Method (_ON) { Method (_ON) {
Store (2, \FLVL) Store (2, \FLVL)
Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
Method (_OFF) { Method (_OFF) {
Store (3, \FLVL) Store (3, \FLVL)
Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
} }
@ -204,12 +204,12 @@ Scope (\_TZ)
} }
Method (_ON) { Method (_ON) {
Store (3, \FLVL) Store (3, \FLVL)
Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
Method (_OFF) { Method (_OFF) {
Store (4, \FLVL) Store (4, \FLVL)
Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
} }
@ -225,12 +225,12 @@ Scope (\_TZ)
} }
Method (_ON) { Method (_ON) {
Store (4, \FLVL) Store (4, \FLVL)
Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
Method (_OFF) { Method (_OFF) {
Store (4, \FLVL) Store (4, \FLVL)
Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
Notify (\_TZ.THRM, 0x81) Notify (\_TZ.THRM, 0x81)
} }
} }