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mb/chausie/ec: Set MS bit in SW02 

Set the MS bit in EC SW02 register to enable s0i3

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Fred Reitberger 2022-06-09 11:04:37 -04:00 committed by Felix Held
parent f9b5665d28
commit f089f9b8c6
1 changed files with 7 additions and 0 deletions
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7
src/mainboard/amd/chausie/ec.c
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@ -26,6 +26,9 @@
#define EC_GPIO_MP2_SEL (1 << 2)
#define EC_GPIO_WWAN_N_LOM_SW (1 << 3)
#define EC_SW02_ADDR 0xB7
#define EC_SW02_MS (1 << 7)
static void configure_ec_gpio(void)
{
uint8_t tmp;
@ -49,6 +52,10 @@ static void configure_ec_gpio(void)
tmp = ec_read(EC_GPIO_C_ADDR);
tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW;
ec_write(EC_GPIO_C_ADDR, tmp);
tmp = ec_read(EC_SW02_ADDR);
tmp |= EC_SW02_MS;
ec_write(EC_SW02_ADDR, tmp);
}
void chausie_ec_init(void)