diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index b1429b6286..b7f56ec53d 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -30,8 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -71,8 +70,7 @@ int clear_recovery_mode_switch(void) int get_write_protect_state(void) { - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); + return 0; } void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index bf70e11e9a..f8ab6fd6bb 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -284,8 +284,8 @@ variant_sleep_gpio_table(size_t *num) static const struct cros_gpio cros_gpios[] = { #if 0 - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), - CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), #endif }; diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index 91a1c038e0..41de87c7ce 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -29,10 +29,6 @@ #define GPE_EC_WAKE GPE0_DW1_06 -/* Write Protect and indication if EC is in RW code. */ -#define GPIO_PCH_WP GPIO_75 -#define GPIO_EC_IN_RW GPIO_41 - /* Memory SKU GPIOs. */ #define MEM_CONFIG3 GPIO_45 #define MEM_CONFIG2 GPIO_38