google/gru: set W2W_DIFFCS_DLY to 5
PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time and there should be more cycles to switch the delay line, so update the W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -279,8 +279,8 @@ struct rk3399_sdram_params params = {
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0x05050502, /* DENALI_CTL_215_DATA */
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0x02080808, /* DENALI_CTL_216_DATA */
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0x02050202, /* DENALI_CTL_217_DATA */
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0x02010202, /* DENALI_CTL_218_DATA */
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0x00010202, /* DENALI_CTL_219_DATA */
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0x02050202, /* DENALI_CTL_218_DATA */
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0x00050202, /* DENALI_CTL_219_DATA */
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0x00020202, /* DENALI_CTL_220_DATA */
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0x02010200, /* DENALI_CTL_221_DATA */
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0x00010201, /* DENALI_CTL_222_DATA */
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@ -279,8 +279,8 @@ struct rk3399_sdram_params params = {
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0x08080803, /* DENALI_CTL_215_DATA */
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0x08080808, /* DENALI_CTL_216_DATA */
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0x02050203, /* DENALI_CTL_217_DATA */
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0x02010303, /* DENALI_CTL_218_DATA */
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0x00010203, /* DENALI_CTL_219_DATA */
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0x02050303, /* DENALI_CTL_218_DATA */
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0x00050203, /* DENALI_CTL_219_DATA */
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0x00020202, /* DENALI_CTL_220_DATA */
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0x03020400, /* DENALI_CTL_221_DATA */
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0x00020401, /* DENALI_CTL_222_DATA */
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@ -279,8 +279,8 @@ struct rk3399_sdram_params params = {
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0x0a0a0a03, /* DENALI_CTL_215_DATA */
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0x08080808, /* DENALI_CTL_216_DATA */
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0x02050103, /* DENALI_CTL_217_DATA */
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0x02010103, /* DENALI_CTL_218_DATA */
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0x00010103, /* DENALI_CTL_219_DATA */
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0x02050103, /* DENALI_CTL_218_DATA */
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0x00050103, /* DENALI_CTL_219_DATA */
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0x00020202, /* DENALI_CTL_220_DATA */
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0x03020500, /* DENALI_CTL_221_DATA */
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0x00020501, /* DENALI_CTL_222_DATA */
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@ -278,9 +278,9 @@ struct rk3399_sdram_params params = {
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0x04040001, /* DENALI_CTL_214_DATA */
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0x0c0c0c04, /* DENALI_CTL_215_DATA */
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0x08080808, /* DENALI_CTL_216_DATA */
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0x02010103, /* DENALI_CTL_217_DATA */
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0x02010103, /* DENALI_CTL_218_DATA */
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0x00010103, /* DENALI_CTL_219_DATA */
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0x02050103, /* DENALI_CTL_217_DATA */
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0x02050103, /* DENALI_CTL_218_DATA */
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0x00050103, /* DENALI_CTL_219_DATA */
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0x00020202, /* DENALI_CTL_220_DATA */
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0x06030600, /* DENALI_CTL_221_DATA */
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0x00030603, /* DENALI_CTL_222_DATA */
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