soc/mediatek/mt8188: Update mtcmos settings for display and audio

- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are
  required.
- For audio, it requires powering on adsp_ao_pwr_con,
  adsp_infra_pwr_con and audio_pwr_con.
- Add new power domain data `ext_buck_iso_bits` for buck isolation
  control.

BUG=b:244208960
TEST=access display registers successfully.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/common/include/soc/mtcmos.h

@@ -8,10 +8,14 @@ struct power_domain_data {
 	u32 pwr_sta_mask;
 	u32 sram_pdn_mask;
 	u32 sram_ack_mask;
+	u32 ext_buck_iso_bits;
 	u32 caps;
 };
 
-#define SCPD_SRAM_ISO	(1U << 0)
+#define SCPD_SRAM_ISO		BIT(0)
+#define SCPD_EXT_BUCK_ISO	BIT(1)
+
+void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd);
 
 void mtcmos_power_on(const struct power_domain_data *pd);
 void mtcmos_adsp_power_on(void);

src/soc/mediatek/common/mtcmos.c

@@ -14,11 +14,19 @@ enum {
 	PWR_RST_B	= 1U << 0
 };
 
+__weak void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd)
+{
+	/* do nothing */
+}
+
 void mtcmos_power_on(const struct power_domain_data *pd)
 {
 	write32(&mtk_spm->poweron_config_set,
 		(SPM_PROJECT_CODE << 16) | (1U << 0));
 
+	if (pd->caps & SCPD_EXT_BUCK_ISO)
+		mtcmos_set_scpd_ext_buck_iso(pd);
+
 	setbits32(pd->pwr_con, PWR_ON);
 	setbits32(pd->pwr_con, PWR_ON_2ND);
 

src/soc/mediatek/mt8188/Makefile.inc

@@ -42,6 +42,7 @@ ramstage-y += ../common/mcupm.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
+ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += soc.c

src/soc/mediatek/mt8188/include/soc/spm.h

@@ -985,30 +985,12 @@ check_member(mtk_spm_regs, spm_pmsr_len_con2, 0xff4);
 static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
 
 static const struct power_domain_data disp[] = {
-	{
-		.pwr_con = &mtk_spm->vppsys0_pwr_con,
-		.pwr_sta_mask = BIT(11),
-		.sram_pdn_mask = BIT(8),
-		.sram_ack_mask = BIT(12),
-	},
 	{
 		.pwr_con = &mtk_spm->vdosys0_pwr_con,
 		.pwr_sta_mask = BIT(13),
 		.sram_pdn_mask = BIT(8),
 		.sram_ack_mask = BIT(12),
 	},
-	{
-		.pwr_con = &mtk_spm->vppsys1_pwr_con,
-		.pwr_sta_mask = BIT(12),
-		.sram_pdn_mask = BIT(8),
-		.sram_ack_mask = BIT(12),
-	},
-	{
-		.pwr_con = &mtk_spm->vdosys1_pwr_con,
-		.pwr_sta_mask = BIT(14),
-		.sram_pdn_mask = BIT(8),
-		.sram_ack_mask = BIT(12),
-	},
 	{
 		.pwr_con = &mtk_spm->edp_tx_pwr_con,
 		.pwr_sta_mask = BIT(17),
@@ -1019,14 +1001,21 @@ static const struct power_domain_data disp[] = {
 
 static const struct power_domain_data audio[] = {
 	{
-		.pwr_con = &mtk_spm->adsp_pwr_con,
+		.pwr_con = &mtk_spm->adsp_ao_pwr_con,
+		.pwr_sta_mask = BIT(10),
+		.ext_buck_iso_bits = BIT(10),
+		.caps = SCPD_EXT_BUCK_ISO,
+	},
+	{
+		.pwr_con = &mtk_spm->adsp_infra_pwr_con,
 		.pwr_sta_mask = BIT(10),
 		.sram_pdn_mask = BIT(8),
 		.sram_ack_mask = BIT(12),
+		.caps = SCPD_SRAM_ISO,
 	},
 	{
 		.pwr_con = &mtk_spm->audio_pwr_con,
-		.pwr_sta_mask = BIT(8),
+		.pwr_sta_mask = BIT(6),
 		.sram_pdn_mask = BIT(8),
 		.sram_ack_mask = BIT(12),
 	},

src/soc/mediatek/mt8188/mtcmos.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/infracfg.h>
+#include <soc/mtcmos.h>
+#include <soc/spm.h>
+
+void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd)
+{
+	clrbits32(&mtk_spm->ext_buck_iso, pd->ext_buck_iso_bits);
+}