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soc/intel/alderlake: Correct Bus and Device of Touch Host Controller 

Correct Bus and Device for THC0 and THC1

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Varshit B Pandya 2021-07-01 16:37:04 +05:30 committed by Subrata Banik
parent ca4e6aa3ad
commit f09b39bf88
2 changed files with 6 additions and 6 deletions
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4
src/soc/intel/alderlake/chipset.cb
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@ -79,8 +79,8 @@ chip soc/intel/alderlake
device pci 0d.2 alias tcss_dma0 off end device pci 0d.2 alias tcss_dma0 off end
device pci 0d.3 alias tcss_dma1 off end device pci 0d.3 alias tcss_dma1 off end
device pci 0e.0 alias vmd off end device pci 0e.0 alias vmd off end
device pci 10.0 alias thc0 off end device pci 10.6 alias thc0 off end
device pci 10.1 alias thc1 off end device pci 10.7 alias thc1 off end
device pci 12.0 alias ish off end device pci 12.0 alias ish off end
device pci 12.6 alias gspi2 off end device pci 12.6 alias gspi2 off end
device pci 13.0 alias gspi3 off end device pci 13.0 alias gspi3 off end

8
src/soc/intel/alderlake/include/soc/pci_devs.h
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@ -79,10 +79,10 @@
/* PCH Devices */ /* PCH Devices */
#define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 #define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0
#define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEV_SLOT_SIO0 0x10
#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0) #define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6)
#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1) #define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7)
#define PCH_DEV_THC0 _PCH_DEV(SIO0, 0) #define PCH_DEV_THC0 _PCH_DEV(SIO0, 6)
#define PCH_DEV_THC1 _PCH_DEV(SIO0, 1) #define PCH_DEV_THC1 _PCH_DEV(SIO0, 7)
#define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEV_SLOT_ISH 0x12
#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)