pcengines/apu1: Fork of amd/persimmon
Drop persimmon customization for superio, azalia, PCI-e reset etc. Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8324 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include "heapManager.h"
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#include "SB800.h"
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#include <stdlib.h>
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/* Call the host environment interface to provide a user hook opportunity. */
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
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// Make sure the right speed settings are selected.
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((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
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return AGESA_SUCCESS;
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}
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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if BOARD_AMD_PERSIMMON
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_4096
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select GFXUMA
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config MAINBOARD_DIR
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string
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default amd/persimmon
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config MAINBOARD_PART_NUMBER
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string
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default "Persimmon"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config MAX_CPUS
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int
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default 2
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config VGA_BIOS
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bool
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default n
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#config VGA_BIOS_FILE
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# string "VGA BIOS path and filename"
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# depends on VGA_BIOS
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# default "rom/video/OntarioGenericVbios.bin"
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config VGA_BIOS_ID
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string
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default "1002,9802"
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config SB800_AHCI_ROM
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bool
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default n
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config DRIVERS_PS2_KEYBOARD
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bool
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default n
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endif # BOARD_AMD_PERSIMMON
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@ -0,0 +1,33 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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ifeq ($(CONFIG_AHCI_BIOS),y)
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stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
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cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
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pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
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pci$(stripped_ahcibios_id).rom-type := optionrom
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endif
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += PlatformGnbPcie.c
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ramstage-y += buildOpts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += PlatformGnbPcie.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* @file
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*
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* IDS Option File
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*
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* This file is used to switch on/off IDS features.
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*
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*/
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#ifndef _OPTION_IDS_H_
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#define _OPTION_IDS_H_
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/**
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*
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* This file generates the defaults tables for the Integrated Debug Support
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* Module. The documented build options are imported from a user controlled
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* file for processing. The build options for the Integrated Debug Support
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* Module are listed below:
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*
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* IDSOPT_IDS_ENABLED
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* IDSOPT_ERROR_TRAP_ENABLED
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* IDSOPT_CONTROL_ENABLED
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* IDSOPT_TRACING_ENABLED
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* IDSOPT_PERF_ANALYSIS
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* IDSOPT_ASSERT_ENABLED
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* IDS_DEBUG_PORT
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* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
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*
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**/
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#define IDSOPT_IDS_ENABLED TRUE
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//#define IDSOPT_TRACING_ENABLED TRUE
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#define IDSOPT_ASSERT_ENABLED TRUE
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//#define IDSOPT_DEBUG_ENABLED FALSE
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//#undef IDSOPT_HOST_SIMNOW
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//#define IDSOPT_HOST_SIMNOW FALSE
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//#undef IDSOPT_HOST_HDT
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//#define IDSOPT_HOST_HDT FALSE
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//#define IDS_DEBUG_PORT 0x80
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#endif
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@ -0,0 +1,143 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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||||
*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "PlatformGnbPcieComplex.h"
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#include <string.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
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#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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{
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AGESA_STATUS Status;
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VOID *BrazosPcieComplexListPtr;
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VOID *BrazosPciePortPtr;
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VOID *BrazosPcieDdiPtr;
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ALLOCATE_HEAP_PARAMS AllocHeapParams;
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PCIe_PORT_DESCRIPTOR PortList [] = {
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// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
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{
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0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
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},
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// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
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{
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0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
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},
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// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
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{
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0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
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},
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// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
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},
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// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
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{
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DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
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}
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};
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PCIe_DDI_DESCRIPTOR DdiList [] = {
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// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
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{
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0, //Descriptor flags
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
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//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
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{ConnectorTypeLvds, Aux1, Hdp1}
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},
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||||
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
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{
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DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
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//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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{ConnectorTypeDP, Aux2, Hdp2}
|
||||
}
|
||||
};
|
||||
|
||||
PCIe_COMPLEX_DESCRIPTOR Brazos = {
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
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0,
|
||||
&PortList[0],
|
||||
&DdiList[0]
|
||||
};
|
||||
|
||||
// GNB PCIe topology Porting
|
||||
|
||||
//
|
||||
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
|
||||
//
|
||||
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
|
||||
|
||||
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
|
||||
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
|
||||
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
|
||||
ASSERT(Status == AGESA_SUCCESS);
|
||||
|
||||
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
|
||||
|
||||
AllocHeapParams.BufferPtr += sizeof(Brazos);
|
||||
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
|
||||
|
||||
AllocHeapParams.BufferPtr += sizeof(PortList);
|
||||
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
|
||||
|
||||
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
|
||||
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
|
||||
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
|
||||
|
||||
|
||||
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
|
||||
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
|
||||
|
||||
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
|
||||
InitEarly->GnbConfig.PsppPolicy = 0;
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
const struct OEM_HOOK OemCustomize = {
|
||||
.InitEarly = OemInitEarly,
|
||||
};
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|
@ -0,0 +1,69 @@
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|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
|
||||
#define _PLATFORM_GNB_PCIE_COMPLEX_H
|
||||
|
||||
#include "Porting.h"
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
|
||||
//GNB GPP Port4
|
||||
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
|
||||
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
|
||||
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
|
||||
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
|
||||
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
|
||||
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
|
||||
|
||||
//GNB GPP Port5
|
||||
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
|
||||
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
|
||||
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
|
||||
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
|
||||
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
|
||||
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
|
||||
|
||||
//GNB GPP Port6
|
||||
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
|
||||
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
|
||||
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
|
||||
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
|
||||
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
|
||||
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
|
||||
|
||||
//GNB GPP Port7
|
||||
#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable
|
||||
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
|
||||
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
|
||||
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
|
||||
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
|
||||
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
|
||||
|
||||
//GNB GPP Port8
|
||||
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
|
||||
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
|
||||
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
|
||||
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
|
||||
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
|
||||
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
|
||||
|
||||
|
||||
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* DBGO("\\_GPE\\_L00\n") */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Legacy PM event */
|
||||
Method(_L08) {
|
||||
/* DBGO("\\_GPE\\_L08\n") */
|
||||
}
|
||||
|
||||
/* Temp warning (TWarn) event */
|
||||
Method(_L09) {
|
||||
/* DBGO("\\_GPE\\_L09\n") */
|
||||
/* Notify (\_TZ.TZ00, 0x80) */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* DBGO("\\_GPE\\_L0B\n") */
|
||||
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* ExtEvent0 SCI event */
|
||||
Method(_L10) {
|
||||
/* DBGO("\\_GPE\\_L10\n") */
|
||||
}
|
||||
|
||||
|
||||
/* ExtEvent1 SCI event */
|
||||
Method(_L11) {
|
||||
/* DBGO("\\_GPE\\_L11\n") */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* DBGO("\\_GPE\\_L18\n") */
|
||||
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Azalia SCI event */
|
||||
Method(_L1B) {
|
||||
/* DBGO("\\_GPE\\_L1B\n") */
|
||||
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
} /* End Scope GPE */
|
||||
|
||||
/* Contains the GPEs for USB overcurrent */
|
||||
#include "usb_oc.asl"
|
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "ide.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
/* Some timing tables */
|
||||
Name(UDTT, Package(){ /* Udma timing table */
|
||||
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||
})
|
||||
|
||||
Name(MDTT, Package(){ /* MWDma timing table */
|
||||
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(POTT, Package(){ /* Pio timing table */
|
||||
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
/* Some timing register value tables */
|
||||
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||
})
|
||||
|
||||
Name(PORT, Package(){
|
||||
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||
})
|
||||
|
||||
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
PPTS, 8, /* Primary PIO Slave Timing */
|
||||
PPTM, 8, /* Primary PIO Master Timing */
|
||||
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||
PPSM, 4, /* Primary PIO slave Mode */
|
||||
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||
PDSM, 4, /* Primary UltraDMA Mode */
|
||||
}
|
||||
|
||||
Method(GTTM, 1) /* get total time*/
|
||||
{
|
||||
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||
Increment(Local0)
|
||||
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||
Increment(Local1)
|
||||
Return(Multiply(30, Add(Local0, Local1)))
|
||||
}
|
||||
|
||||
Device(PRID)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
Method(_GTM, 0, Serialized)
|
||||
{
|
||||
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||
|
||||
/* Just return if the channel is disabled */
|
||||
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||
Return(OTBF)
|
||||
}
|
||||
|
||||
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||
Or(BFFG, 0x1A, BFFG)
|
||||
|
||||
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||
|
||||
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x01, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||
Or(BFFG, 0x04, BFFG)
|
||||
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||
}
|
||||
Else {
|
||||
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||
}
|
||||
|
||||
Return(OTBF) /* out buffer */
|
||||
} /* End Method(_GTM) */
|
||||
|
||||
Method(_STM, 3, Serialized)
|
||||
{
|
||||
NAME(INBF, Buffer(20) { /* in buffer */
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF,
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||
|
||||
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||
|
||||
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||
|
||||
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDMM,)
|
||||
Or(PDCR, 0x01, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||
}
|
||||
}
|
||||
|
||||
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Divide(Local0, 7, PDSM,)
|
||||
Or(PDCR, 0x02, PDCR)
|
||||
}
|
||||
Else {
|
||||
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||
}
|
||||
}
|
||||
/* Return(INBF) */
|
||||
} /*End Method(_STM) */
|
||||
Device(MST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTF, 0, Serialized) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF, 0, Serialized) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Data to be patched by the BIOS during POST */
|
||||
/* FIXME the patching is not done yet! */
|
||||
/* Memory related values */
|
||||
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
|
||||
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
|
||||
Name(PBLN, 0x0) /* Length of BIOS area */
|
||||
|
||||
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
|
||||
Name(HPBA, 0xFED00000) /* Base address of HPET table */
|
||||
|
||||
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
|
||||
|
||||
/* Some global data */
|
||||
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
|
||||
Name(OSV, Ones) /* Assume nothing */
|
||||
Name(PMOD, One) /* Assume APIC */
|
||||
|
||||
Scope(\_SB) {
|
||||
Method(OSFL, 0){
|
||||
|
||||
if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
|
||||
|
||||
if(CondRefOf(\_OSI,Local1))
|
||||
{
|
||||
Store(1, OSVR) /* Assume some form of XP */
|
||||
if (\_OSI("Windows 2006")) /* Vista */
|
||||
{
|
||||
Store(2, OSVR)
|
||||
}
|
||||
} else {
|
||||
If(WCMP(\_OS,"Linux")) {
|
||||
Store(3, OSVR) /* Linux */
|
||||
} Else {
|
||||
Store(4, OSVR) /* Gotta be WinCE */
|
||||
}
|
||||
}
|
||||
Return(OSVR)
|
||||
}
|
||||
}
|
||||
|
||||
Scope(\_SI) {
|
||||
Method(_SST, 1) {
|
||||
/* DBGO("\\_SI\\_SST\n") */
|
||||
/* DBGO(" New Indicator state: ") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
}
|
||||
} /* End Scope SI */
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, INTC, 0 },
|
||||
Package(){0x0001FFFF, 1, INTD, 0 },
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, INTD, 0 },
|
||||
Package(){0x0003FFFF, 1, INTA, 0 },
|
||||
Package(){0x0003FFFF, 2, INTB, 0 },
|
||||
Package(){0x0003FFFF, 3, INTC, 0 },
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
Package(){0x0005FFFF, 0, INTB, 0 },
|
||||
Package(){0x0005FFFF, 1, INTC, 0 },
|
||||
Package(){0x0005FFFF, 2, INTD, 0 },
|
||||
Package(){0x0005FFFF, 3, INTA, 0 },
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
/* OHCI, dev 18, 19, 22 func 0
|
||||
* EHCI, dev 18, 19, 22 func 2 */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */
|
||||
Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
Package(){0x0015FFFF, 0, INTA, 0 },
|
||||
Package(){0x0015FFFF, 1, INTB, 0 },
|
||||
Package(){0x0015FFFF, 2, INTC, 0 },
|
||||
Package(){0x0015FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, 0, 18 },
|
||||
Package(){0x0001FFFF, 1, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
Package(){0x0003FFFF, 1, 0, 16 },
|
||||
Package(){0x0003FFFF, 2, 0, 17 },
|
||||
Package(){0x0003FFFF, 3, 0, 18 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
Package(){0x0004FFFF, 1, 0, 17 },
|
||||
Package(){0x0004FFFF, 2, 0, 18 },
|
||||
Package(){0x0004FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
Package(){0x0005FFFF, 0, 0, 17 },
|
||||
Package(){0x0005FFFF, 1, 0, 18 },
|
||||
Package(){0x0005FFFF, 2, 0, 19 },
|
||||
Package(){0x0005FFFF, 3, 0, 16 },
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
Package(){0x0006FFFF, 0, 0, 18 },
|
||||
Package(){0x0006FFFF, 1, 0, 19 },
|
||||
Package(){0x0006FFFF, 2, 0, 16 },
|
||||
Package(){0x0006FFFF, 3, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
Package(){0x0007FFFF, 0, 0, 19 },
|
||||
Package(){0x0007FFFF, 1, 0, 16 },
|
||||
Package(){0x0007FFFF, 2, 0, 17 },
|
||||
Package(){0x0007FFFF, 3, 0, 18 },
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
/* OHCI, dev 18, 19, 22 func 0
|
||||
* EHCI, dev 18, 19, 22 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
|
||||
/* TODO: pcie */
|
||||
Package(){0x0015FFFF, 0, 0, 16 },
|
||||
Package(){0x0015FFFF, 1, 0, 17 },
|
||||
Package(){0x0015FFFF, 2, 0, 18 },
|
||||
Package(){0x0015FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
|
||||
Package(){0x0003FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0003FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0003FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0003FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0004FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0004FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0004FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0004FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
Method(\_PTS, 1) {
|
||||
/* DBGO("\\_PTS\n") */
|
||||
/* DBGO("From S0 to S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
/* Don't allow PCIRST# to reset USB */
|
||||
if (LEqual(Arg0,3)){
|
||||
Store(0,URRE)
|
||||
}
|
||||
|
||||
/* Clear sleep SMI status flag and enable sleep SMI trap. */
|
||||
/*Store(One, CSSM)
|
||||
Store(One, SSEN)*/
|
||||
|
||||
/* On older chips, clear PciExpWakeDisEn */
|
||||
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
|
||||
* Store(0,\_SB.PWDE)
|
||||
*}
|
||||
*/
|
||||
|
||||
/* Clear wake status structure. */
|
||||
Store(0, Index(WKST,0))
|
||||
Store(0, Index(WKST,1))
|
||||
} /* End Method(\_PTS) */
|
||||
|
||||
/*
|
||||
* \_BFS OEM Back From Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*/
|
||||
Method(\_BFS, 1) {
|
||||
/* DBGO("\\_BFS\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
}
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* DBGO("\\_WAK\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
|
||||
/* Re-enable HPET */
|
||||
Store(1,HPDE)
|
||||
|
||||
/* Restore PCIRST# so it resets USB */
|
||||
if (LEqual(Arg0,3)){
|
||||
Store(1,URRE)
|
||||
}
|
||||
|
||||
/* Arbitrarily clear PciExpWakeStatus */
|
||||
Store(PWST, PWST)
|
||||
|
||||
/* if(DeRefOf(Index(WKST,0))) {
|
||||
* Store(0, Index(WKST,1))
|
||||
* } else {
|
||||
* Store(Arg0, Index(WKST,1))
|
||||
* }
|
||||
*/
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* No Super I/O device or functionality yet */
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Thermal Zones have been #if 0 for a long time.
|
||||
* Removing it for now because it doesn't seem to
|
||||
* do anything when enabled anyway.
|
||||
*/
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* USB overcurrent mapping pins. */
|
||||
Name(UOM0, 0)
|
||||
Name(UOM1, 2)
|
||||
Name(UOM2, 0)
|
||||
Name(UOM3, 7)
|
||||
Name(UOM4, 2)
|
||||
Name(UOM5, 2)
|
||||
Name(UOM6, 6)
|
||||
Name(UOM7, 2)
|
||||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/amdfam14.h>
|
||||
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB800 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
|
@ -0,0 +1,5 @@
|
|||
Board name: DBFT1-00-EVAL-KT (Persimmon)
|
||||
Category: eval
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
|
@ -0,0 +1,453 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD User options selection for a Brazos platform solution system
|
||||
*
|
||||
* This file is placed in the user's platform directory and contains the
|
||||
* build option selections desired for that platform.
|
||||
*
|
||||
* For Information about this file, see @ref platforminstall.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "Filecode.h"
|
||||
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
|
||||
|
||||
|
||||
/* Select the cpu family. */
|
||||
#define INSTALL_FAMILY_10_SUPPORT FALSE
|
||||
#define INSTALL_FAMILY_12_SUPPORT FALSE
|
||||
#define INSTALL_FAMILY_14_SUPPORT TRUE
|
||||
#define INSTALL_FAMILY_15_SUPPORT FALSE
|
||||
|
||||
/* Select the cpu socket type. */
|
||||
#define INSTALL_G34_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_C32_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_FM1_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_FP1_SOCKET_SUPPORT FALSE
|
||||
#define INSTALL_FT1_SOCKET_SUPPORT TRUE
|
||||
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
|
||||
|
||||
/*
|
||||
* Agesa optional capabilities selection.
|
||||
* Uncomment and mark FALSE those features you wish to include in the build.
|
||||
* Comment out or mark TRUE those features you want to REMOVE from the build.
|
||||
*/
|
||||
|
||||
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
|
||||
|
||||
#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
|
||||
|
||||
#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
|
||||
//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
|
||||
#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
|
||||
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
|
||||
#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
|
||||
#define BLDOPT_REMOVE_DQS_TRAINING FALSE
|
||||
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
|
||||
#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
|
||||
#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
|
||||
#define BLDOPT_REMOVE_SRAT FALSE
|
||||
#define BLDOPT_REMOVE_SLIT FALSE
|
||||
#define BLDOPT_REMOVE_WHEA FALSE
|
||||
#define BLDOPT_REMOVE_DMI TRUE
|
||||
#define BLDOPT_REMOVE_HT_ASSIST TRUE
|
||||
#define BLDOPT_REMOVE_ATM_MODE TRUE
|
||||
//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
|
||||
//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
|
||||
#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
|
||||
//#define BLDOPT_REMOVE_C6_STATE TRUE
|
||||
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
|
||||
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
|
||||
|
||||
/*
|
||||
* Agesa entry points used in this implementation.
|
||||
*/
|
||||
#define AGESA_ENTRY_INIT_RESET TRUE
|
||||
#define AGESA_ENTRY_INIT_RECOVERY FALSE
|
||||
#define AGESA_ENTRY_INIT_EARLY TRUE
|
||||
#define AGESA_ENTRY_INIT_POST TRUE
|
||||
#define AGESA_ENTRY_INIT_ENV TRUE
|
||||
#define AGESA_ENTRY_INIT_MID TRUE
|
||||
#define AGESA_ENTRY_INIT_LATE TRUE
|
||||
#define AGESA_ENTRY_INIT_S3SAVE TRUE
|
||||
#define AGESA_ENTRY_INIT_RESUME TRUE
|
||||
#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
|
||||
#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
|
||||
|
||||
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
|
||||
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
|
||||
|
||||
#define BLDCFG_VRM_CURRENT_LIMIT 24000
|
||||
//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
|
||||
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
|
||||
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
|
||||
#define BLDCFG_VRM_SLEW_RATE 5000
|
||||
//#define BLDCFG_VRM_NB_SLEW_RATE 5000
|
||||
//#define BLDCFG_VRM_ADDITIONAL_DELAY 0
|
||||
//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
|
||||
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
|
||||
//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
|
||||
#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
|
||||
//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
|
||||
|
||||
//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
|
||||
//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
|
||||
//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
|
||||
#define BLDCFG_PLAT_NUM_IO_APICS 3
|
||||
//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
|
||||
//#define BLDCFG_PLATFORM_C1E_OPDATA 0
|
||||
//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
|
||||
//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
|
||||
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
|
||||
#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
|
||||
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
|
||||
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
|
||||
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
|
||||
#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
//#define BLDCFG_STARTING_BUSNUM 0
|
||||
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
|
||||
//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
|
||||
//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
|
||||
//#define BLDCFG_BUID_SWAP_LIST 0
|
||||
//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
|
||||
//#define BLDCFG_HTFABRIC_LIMITS_LIST 0
|
||||
//#define BLDCFG_HTCHAIN_LIMITS_LIST 0
|
||||
//#define BLDCFG_BUS_NUMBERS_LIST 0
|
||||
//#define BLDCFG_IGNORE_LINK_LIST 0
|
||||
//#define BLDCFG_LINK_SKIP_REGANG_LIST 0
|
||||
//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
|
||||
//#define BLDCFG_USE_HT_ASSIST TRUE
|
||||
//#define BLDCFG_USE_ATM_MODE TRUE
|
||||
//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
|
||||
#define BLDCFG_S3_LATE_RESTORE TRUE
|
||||
//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
|
||||
//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
|
||||
//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
|
||||
//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
|
||||
//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
|
||||
//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
|
||||
#define BLDCFG_CFG_GNB_HD_AUDIO FALSE
|
||||
//#define BLDCFG_CFG_ABM_SUPPORT FALSE
|
||||
//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
|
||||
//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
|
||||
//#define BLDCFG_MEM_INIT_PSTATE 0
|
||||
//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
|
||||
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
|
||||
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
|
||||
//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
|
||||
//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
|
||||
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_POWER_DOWN TRUE
|
||||
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
|
||||
//#define BLDCFG_ONLINE_SPARE FALSE
|
||||
//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
|
||||
#define BLDCFG_BANK_SWIZZLE TRUE
|
||||
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
|
||||
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
|
||||
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
|
||||
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
|
||||
#define BLDCFG_USE_BURST_MODE FALSE
|
||||
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
|
||||
//#define BLDCFG_ENABLE_ECC_FEATURE TRUE
|
||||
//#define BLDCFG_ECC_REDIRECTION FALSE
|
||||
//#define BLDCFG_SCRUB_DRAM_RATE 0
|
||||
//#define BLDCFG_SCRUB_L2_RATE 0
|
||||
//#define BLDCFG_SCRUB_L3_RATE 0
|
||||
//#define BLDCFG_SCRUB_IC_RATE 0
|
||||
//#define BLDCFG_SCRUB_DC_RATE 0
|
||||
//#define BLDCFG_ECC_SYNC_FLOOD 0
|
||||
//#define BLDCFG_ECC_SYMBOL_SIZE 0
|
||||
//#define BLDCFG_1GB_ALIGN FALSE
|
||||
#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
|
||||
#define BLDCFG_UMA_ALLOCATION_SIZE 0
|
||||
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
|
||||
#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
|
||||
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
|
||||
#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
|
||||
|
||||
/*
|
||||
* Agesa configuration values selection.
|
||||
* Uncomment and specify the value for the configuration options
|
||||
* needed by the system.
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "CommonReturns.h"
|
||||
|
||||
/* The fixed MTRR values to be set after memory initialization. */
|
||||
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
||||
{
|
||||
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
|
||||
{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
|
||||
{ CPU_LIST_TERMINAL }
|
||||
};
|
||||
|
||||
/* Include the files that instantiate the configuration definitions. */
|
||||
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Define the RELEASE VERSION string
|
||||
*
|
||||
* The Release Version string should identify the next planned release.
|
||||
* When a branch is made in preparation for a release, the release manager
|
||||
* should change/confirm that the branch version of this file contains the
|
||||
* string matching the desired version for the release. The trunk version of
|
||||
* the file should always contain a trailing 'X'. This will make sure that a
|
||||
* development build from trunk will not be confused for a released version.
|
||||
* The release manager will need to remove the trailing 'X' and update the
|
||||
* version string as appropriate for the release. The trunk copy of this file
|
||||
* should also be updated/incremented for the next expected version, + trailing 'X'
|
||||
****************************************************************************/
|
||||
// This is the delivery package title, "BrazosPI"
|
||||
// This string MUST be exactly 8 characters long
|
||||
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
|
||||
|
||||
// This is the release version number of the AGESA component
|
||||
// This string MUST be exactly 12 characters long
|
||||
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
|
||||
|
||||
/* MEMORY_BUS_SPEED */
|
||||
#define DDR400_FREQUENCY 200 ///< DDR 400
|
||||
#define DDR533_FREQUENCY 266 ///< DDR 533
|
||||
#define DDR667_FREQUENCY 333 ///< DDR 667
|
||||
#define DDR800_FREQUENCY 400 ///< DDR 800
|
||||
#define DDR1066_FREQUENCY 533 ///< DDR 1066
|
||||
#define DDR1333_FREQUENCY 667 ///< DDR 1333
|
||||
#define DDR1600_FREQUENCY 800 ///< DDR 1600
|
||||
#define DDR1866_FREQUENCY 933 ///< DDR 1866
|
||||
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
|
||||
|
||||
/* QUANDRANK_TYPE*/
|
||||
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
|
||||
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
|
||||
|
||||
/* USER_MEMORY_TIMING_MODE */
|
||||
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
|
||||
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
|
||||
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
|
||||
|
||||
/* POWER_DOWN_MODE */
|
||||
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
|
||||
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
|
||||
|
||||
// The following definitions specify the default values for various parameters in which there are
|
||||
// no clearly defined defaults to be used in the common file. The values below are based on product
|
||||
// and BKDG content, please consult the AGESA Memory team for consultation.
|
||||
#define DFLT_SCRUB_DRAM_RATE (0)
|
||||
#define DFLT_SCRUB_L2_RATE (0)
|
||||
#define DFLT_SCRUB_L3_RATE (0)
|
||||
#define DFLT_SCRUB_IC_RATE (0)
|
||||
#define DFLT_SCRUB_DC_RATE (0)
|
||||
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define DFLT_VRM_SLEW_RATE (5000)
|
||||
|
||||
// Instantiate all solution relevant data.
|
||||
#include "PlatformInstall.h"
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CUSTOMER OVERIDES MEMORY TABLE
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
|
||||
//
|
||||
// The following macros are supported (use comma to separate macros):
|
||||
//
|
||||
// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
|
||||
// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
|
||||
// AGESA will base on this value to disable unused MemClk to save power.
|
||||
// Example:
|
||||
// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
|
||||
// Bit AM3/S1g3 pin name
|
||||
// 0 M[B,A]_CLK_H/L[0]
|
||||
// 1 M[B,A]_CLK_H/L[1]
|
||||
// 2 M[B,A]_CLK_H/L[2]
|
||||
// 3 M[B,A]_CLK_H/L[3]
|
||||
// 4 M[B,A]_CLK_H/L[4]
|
||||
// 5 M[B,A]_CLK_H/L[5]
|
||||
// 6 M[B,A]_CLK_H/L[6]
|
||||
// 7 M[B,A]_CLK_H/L[7]
|
||||
// And platform has the following routing:
|
||||
// CS0 M[B,A]_CLK_H/L[4]
|
||||
// CS1 M[B,A]_CLK_H/L[2]
|
||||
// CS2 M[B,A]_CLK_H/L[3]
|
||||
// CS3 M[B,A]_CLK_H/L[5]
|
||||
// Then platform can specify the following macro:
|
||||
// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
|
||||
//
|
||||
// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
|
||||
// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
|
||||
// AGESA will base on this value to tristate unused CKE to save power.
|
||||
//
|
||||
// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
|
||||
// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
|
||||
// AGESA will base on this value to tristate unused ODT pins to save power.
|
||||
//
|
||||
// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
|
||||
// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
|
||||
// AGESA will base on this value to tristate unused Chip select to save power.
|
||||
//
|
||||
// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
|
||||
// Specifies the number of DIMM slots per channel.
|
||||
//
|
||||
// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
|
||||
// Specifies the number of Chip selects per channel.
|
||||
//
|
||||
// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
|
||||
// Specifies the number of channels per socket.
|
||||
//
|
||||
// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
|
||||
// Specifies DDR bus speed of channel ChannelID on socket SocketID.
|
||||
//
|
||||
// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
|
||||
// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
|
||||
//
|
||||
// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
|
||||
// Byte6Seed, Byte7Seed, ByteEccSeed)
|
||||
// Specifies the write leveling seed for a channel of a socket.
|
||||
//
|
||||
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
|
||||
PSO_END
|
||||
};
|
||||
|
||||
/*
|
||||
* These tables are optional and may be used to adjust memory timing settings
|
||||
*/
|
||||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
|
||||
//DA Customer table
|
||||
CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
|
||||
{
|
||||
// Hardcoded Memory Training Values
|
||||
|
||||
// The following macro should be used to override training values for your platform
|
||||
//
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
|
||||
//
|
||||
// NOTE:
|
||||
// The following training hardcode values are example values that were taken from a tilapia motherboard
|
||||
// with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
|
||||
// the table and replace the byte lane values with your own.
|
||||
//
|
||||
// ------------------ BYTE LANES ----------------------
|
||||
// BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
|
||||
// Write Data Timing
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
|
||||
|
||||
// DQS Receiver Enable
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
|
||||
|
||||
// Write DQS Delays
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
|
||||
|
||||
// Read DQS Delays
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
|
||||
//--------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
// TABLE END
|
||||
NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
|
||||
};
|
||||
CONST UINT8 SizeOfTableON = ARRAY_SIZE(AGESA_MEM_TABLE_ON);
|
||||
|
||||
/* ***************************************************************************
|
||||
* Optional User code to be included into the AGESA build
|
||||
* These may be 32-bit call-out routines...
|
||||
*/
|
||||
//AGESA_STATUS
|
||||
//AgesaReadSpd (
|
||||
// IN UINTN FcnData,
|
||||
// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
|
||||
// )
|
||||
//{
|
||||
// /* platform code to read an SPD... */
|
||||
// return Status;
|
||||
//}
|
|
@ -0,0 +1,89 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
chip northbridge/amd/agesa/family14/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family14
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1510 inherit
|
||||
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
|
||||
# device pci 18.0 on # northbridge
|
||||
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
|
||||
device pci 4.0 on end # PCIE P2P bridge on-board NIC
|
||||
device pci 5.0 off end # PCIE P2P bridge
|
||||
device pci 6.0 on end # PCIE P2P bridge PCIe slot
|
||||
device pci 7.0 off end # PCIE P2P bridge
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
end # agesa northbridge
|
||||
|
||||
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # OHCI USB 0-4
|
||||
device pci 12.2 on end # EHCI USB 0-4
|
||||
device pci 13.0 on end # OHCI USB 5-9
|
||||
device pci 13.2 on end # EHCI USB 5-9
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
|
||||
device pci 14.5 off end # OHCI FS/LS USB
|
||||
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
|
||||
device pci 15.0 off end # PCIe PortA
|
||||
device pci 15.1 off end # PCIe PortB
|
||||
device pci 15.2 off end # PCIe PortC
|
||||
device pci 15.3 off end # PCIe PortD
|
||||
device pci 16.0 off end # OHCI USB 10-13
|
||||
device pci 16.2 off end # EHCI USB 10-13
|
||||
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
|
||||
end #southbridge/amd/cimx/sb800
|
||||
# end # device pci 18.0
|
||||
# These seem unnecessary
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
device pci 18.6 on end
|
||||
device pci 18.7 on end
|
||||
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
|
||||
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family14/root_complex
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"AMD ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
#include <cpu/amd/agesa/family14/acpi/cpu.asl>
|
||||
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Scope(\_SB) {
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
Device(PCI0) {
|
||||
|
||||
/* Describe the AMD Northbridge */
|
||||
#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
|
||||
|
||||
/* Describe the AMD Fusion Controller Hub Southbridge */
|
||||
#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
|
||||
|
||||
/* Primary (and only) IDE channel */
|
||||
Device(IDEC) {
|
||||
Name(_ADR, 0x00140001)
|
||||
#include "acpi/ide.asl"
|
||||
} /* end IDEC */
|
||||
|
||||
}
|
||||
} /* End Scope(_SB) */
|
||||
|
||||
/* Contains the supported sleep states for this chipset */
|
||||
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
|
||||
|
||||
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
|
||||
#include "acpi/sleep.asl"
|
||||
|
||||
#include "acpi/gpe.asl"
|
||||
#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
|
||||
#include "acpi/thermal.asl"
|
||||
}
|
||||
/* End of ASL file */
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam14.h>
|
||||
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
|
||||
|
||||
|
||||
slot_num++;
|
||||
|
||||
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
|
||||
}
|
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <southbridge/amd/amd_pci_util.h>
|
||||
#include <southbridge/amd/cimx/cimx_util.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <northbridge/amd/agesa/BiosCallOuts.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include "SBPLATFORM.h"
|
||||
#include <southbridge/amd/cimx/sb800/pci_devs.h>
|
||||
#include <northbridge/amd/agesa/family14/pci_devs.h>
|
||||
|
||||
void set_pcie_reset(void);
|
||||
void set_pcie_dereset(void);
|
||||
|
||||
/***********************************************************
|
||||
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
|
||||
* This table is responsible for physically routing the PIC and
|
||||
* IOAPIC IRQs to the different PCI devices on the system. It
|
||||
* is read and written via registers 0xC00/0xC01 as an
|
||||
* Index/Data pair. These values are chipset and mainboard
|
||||
* dependent and should be updated accordingly.
|
||||
*
|
||||
* These values are used by the PCI configuration space,
|
||||
* MP Tables. TODO: Make ACPI use these values too.
|
||||
*
|
||||
* The Persimmon PCI INTA/B/C/D pins are connected to
|
||||
* FCH pins INTE/F/G/H on the schematic so these need
|
||||
* to be routed as well.
|
||||
*/
|
||||
static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/20/22 INTA-C */
|
||||
[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
|
||||
/* IDE, SATA */
|
||||
[0x40] = 0x0B,0x0B,
|
||||
/* GPPInt0 - 3 */
|
||||
[0x50] = 0x0A,0x0B,0x0A,0x0B
|
||||
};
|
||||
|
||||
static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
|
||||
[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/22/20 INTA-C */
|
||||
[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
|
||||
/* IDE, SATA */
|
||||
[0x40] = 0x11,0x13,
|
||||
/* GPPInt0 - 3 */
|
||||
[0x50] = 0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
/*
|
||||
* This table defines the index into the picr/intr_data
|
||||
* tables for each device. Any enabled device and slot
|
||||
* that uses hardware interrupts should have an entry
|
||||
* in this table to define its index into the FCH
|
||||
* PCI_INTR register 0xC00/0xC01. This index will define
|
||||
* the interrupt that it should use. Putting PIRQ_A into
|
||||
* the PIN A index for a device will tell that device to
|
||||
* use PIC IRQ 10 if it uses PIN A for its hardware INT.
|
||||
*/
|
||||
/*
|
||||
* Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
|
||||
* but because PCI INT_PIN swizzling isnt implemented to match
|
||||
* the IDSEL (dev 3) of the slot, the table is adjusted for the
|
||||
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
|
||||
* off-chip devices should get mapped to PIRQH/E/F/G.
|
||||
*/
|
||||
static const struct pirq_struct mainboard_pirq_data[] = {
|
||||
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
|
||||
{GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
|
||||
{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */
|
||||
{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */
|
||||
{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
|
||||
{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
|
||||
{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
|
||||
{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
|
||||
{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
|
||||
{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
|
||||
{IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */
|
||||
{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
|
||||
{SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */
|
||||
{OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */
|
||||
{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
|
||||
{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
pirq_data_ptr = mainboard_pirq_data;
|
||||
pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* TODO
|
||||
* SB CIMx callback
|
||||
*/
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* TODO
|
||||
* mainboard specific SB CIMx callback
|
||||
*/
|
||||
void set_pcie_dereset(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/**********************************************
|
||||
* Enable the dedicated functions of the board.
|
||||
**********************************************/
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
|
||||
/* Initialize the PIRQ data structures for consumption */
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam14.h>
|
||||
#include <SBPLATFORM.h>
|
||||
#include <southbridge/amd/amd_pci_util.h>
|
||||
#include <drivers/generic/ioapic/chip.h>
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
/* Intialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* LPC */
|
||||
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* IDE */
|
||||
PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
|
||||
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
|
||||
|
||||
/* PCI slots */
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PLATFORM_CFG_H_
|
||||
#define _PLATFORM_CFG_H_
|
||||
|
||||
/**
|
||||
* @def BIOS_SIZE
|
||||
* BIOS_SIZE_{1,2,4,8,16}M
|
||||
*
|
||||
* In SB800, default ROM size is 1M Bytes, if your platform ROM
|
||||
* bigger than 1M you have to set the ROM size outside CIMx module and
|
||||
* before AGESA module get call.
|
||||
*/
|
||||
#ifndef BIOS_SIZE
|
||||
#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
|
||||
#endif /* BIOS_SIZE */
|
||||
|
||||
/**
|
||||
* @def SPREAD_SPECTRUM
|
||||
* @brief
|
||||
* 0 - Disable Spread Spectrum function
|
||||
* 1 - Enable Spread Spectrum function
|
||||
*/
|
||||
#define SPREAD_SPECTRUM 0
|
||||
|
||||
/**
|
||||
* @def SB_HPET_TIMER
|
||||
* @brief
|
||||
* 0 - Disable hpet
|
||||
* 1 - Enable hpet
|
||||
*/
|
||||
#define HPET_TIMER 1
|
||||
|
||||
/**
|
||||
* @def USB_CONFIG
|
||||
* @brief bit[0-6] used to control USB
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
* Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
|
||||
* Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
|
||||
* Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
|
||||
* Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
|
||||
* Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
|
||||
* Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
|
||||
* Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
|
||||
*/
|
||||
#define USB_CONFIG 0x7F
|
||||
|
||||
/**
|
||||
* @def PCI_CLOCK_CTRL
|
||||
* @brief bit[0-4] used for PCI Slots Clock Control,
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
* PCI SLOT 0 define at BIT0
|
||||
* PCI SLOT 1 define at BIT1
|
||||
* PCI SLOT 2 define at BIT2
|
||||
* PCI SLOT 3 define at BIT3
|
||||
* PCI SLOT 4 define at BIT4
|
||||
*/
|
||||
#define PCI_CLOCK_CTRL 0x07
|
||||
|
||||
/**
|
||||
* @def SATA_CONTROLLER
|
||||
* @brief INCHIP Sata Controller
|
||||
*/
|
||||
#define SATA_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def SATA_MODE
|
||||
* @brief INCHIP Sata Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_MODE CONFIG_SB800_SATA_MODE
|
||||
|
||||
/**
|
||||
* @brief INCHIP Sata IDE Controller Mode
|
||||
*/
|
||||
#define IDE_LEGACY_MODE 0
|
||||
#define IDE_NATIVE_MODE 1
|
||||
|
||||
/**
|
||||
* @def SATA_IDE_MODE
|
||||
* @brief INCHIP Sata IDE Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_IDE_MODE IDE_LEGACY_MODE
|
||||
|
||||
/**
|
||||
* @def EXTERNAL_CLOCK
|
||||
* @brief 00/10: Reference clock from crystal oscillator via
|
||||
* PAD_XTALI and PAD_XTALO
|
||||
*
|
||||
* @def INTERNAL_CLOCK
|
||||
* @brief 01/11: Reference clock from internal clock through
|
||||
* CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
|
||||
*/
|
||||
#define EXTERNAL_CLOCK 0x00
|
||||
#define INTERNAL_CLOCK 0x01
|
||||
|
||||
/* NOTE: inagua have to using internal clock,
|
||||
* otherwise can not detect sata drive
|
||||
*/
|
||||
#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
|
||||
|
||||
/**
|
||||
* @def SATA_PORT_MULT_CAP_RESERVED
|
||||
* @brief 1 ON, 0 0FF
|
||||
*/
|
||||
#define SATA_PORT_MULT_CAP_RESERVED 1
|
||||
|
||||
|
||||
/**
|
||||
* @def AZALIA_AUTO
|
||||
* @brief Detect Azalia controller automatically.
|
||||
*
|
||||
* @def AZALIA_DISABLE
|
||||
* @brief Disable Azalia controller.
|
||||
|
||||
* @def AZALIA_ENABLE
|
||||
* @brief Enable Azalia controller.
|
||||
*/
|
||||
#define AZALIA_AUTO 0
|
||||
#define AZALIA_DISABLE 1
|
||||
#define AZALIA_ENABLE 2
|
||||
|
||||
/**
|
||||
* @brief INCHIP HDA controller
|
||||
*/
|
||||
#define AZALIA_CONTROLLER AZALIA_AUTO
|
||||
|
||||
/**
|
||||
* @def AZALIA_PIN_CONFIG
|
||||
* @brief
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
*/
|
||||
#define AZALIA_PIN_CONFIG 1
|
||||
|
||||
/**
|
||||
* @def AZALIA_SDIN_PIN
|
||||
* @brief
|
||||
* SDIN0 is define at BIT0 & BIT1
|
||||
* 00 - GPIO PIN
|
||||
* 01 - Reserved
|
||||
* 10 - As a Azalia SDIN pin
|
||||
* SDIN1 is define at BIT2 & BIT3
|
||||
* SDIN2 is define at BIT4 & BIT5
|
||||
* SDIN3 is define at BIT6 & BIT7
|
||||
*/
|
||||
//#define AZALIA_SDIN_PIN 0xAA
|
||||
#define AZALIA_SDIN_PIN 0x2A
|
||||
|
||||
/**
|
||||
* @def GPP_CONTROLLER
|
||||
*/
|
||||
#define GPP_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def GPP_CFGMODE
|
||||
* @brief GPP Link Configuration
|
||||
* four possible configuration:
|
||||
* GPP_CFGMODE_X4000
|
||||
* GPP_CFGMODE_X2200
|
||||
* GPP_CFGMODE_X2110
|
||||
* GPP_CFGMODE_X1111
|
||||
*/
|
||||
#define GPP_CFGMODE GPP_CFGMODE_X1111
|
||||
|
||||
/**
|
||||
* @def NB_SB_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define NB_SB_GEN2 TRUE
|
||||
|
||||
/**
|
||||
* @def SB_GPP_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define SB_GPP_GEN2 TRUE
|
||||
|
||||
/**
|
||||
* @def SB_GPP_UNHIDE_PORTS
|
||||
* TRUE - ports visible always, even port empty
|
||||
* FALSE - ports invisible if port empty
|
||||
*/
|
||||
#define SB_GPP_UNHIDE_PORTS FALSE
|
||||
|
||||
/**
|
||||
* @def GEC_CONFIG
|
||||
* 0 - Enable
|
||||
* 1 - Disable
|
||||
*/
|
||||
#define GEC_CONFIG 0
|
||||
|
||||
/* set up an ACPI preferred power management profile */
|
||||
/* from acpi.h
|
||||
* PM_UNSPECIFIED = 0,
|
||||
* PM_DESKTOP = 1,
|
||||
* PM_MOBILE = 2,
|
||||
* PM_WORKSTATION = 3,
|
||||
* PM_ENTERPRISE_SERVER = 4,
|
||||
* PM_SOHO_SERVER = 5,
|
||||
* PM_APPLIANCE_PC = 6,
|
||||
* PM_PERFORMANCE_SERVER = 7,
|
||||
* PM_TABLET = 8
|
||||
*/
|
||||
#define FADT_PM_PROFILE 1
|
||||
|
||||
#endif /* _PLATFORM_CFG_H_ */
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/stages.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <console/loglevel.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <northbridge/amd/agesa/agesawrapper.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <sb_cimx.h>
|
||||
#include "SBPLATFORM.h"
|
||||
#include "cbmem.h"
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* All cores: allow caching of flash chip code and data
|
||||
* (there are no cache-as-ram reliability concerns with family 14h)
|
||||
*/
|
||||
__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
|
||||
__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
|
||||
|
||||
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
|
||||
__writemsr (0xc0010062, 0);
|
||||
|
||||
amd_initmmio();
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
post_code(0x30);
|
||||
sb_Poweron_Init();
|
||||
|
||||
post_code(0x31);
|
||||
console_init();
|
||||
}
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
post_code(0x34);
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Load MPB */
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
|
||||
|
||||
post_code(0x37);
|
||||
agesawrapper_amdinitreset();
|
||||
|
||||
post_code(0x39);
|
||||
agesawrapper_amdinitearly();
|
||||
|
||||
int s3resume = acpi_is_wakeup_s3();
|
||||
if (!s3resume) {
|
||||
post_code(0x40);
|
||||
agesawrapper_amdinitpost();
|
||||
|
||||
post_code(0x42);
|
||||
agesawrapper_amdinitenv();
|
||||
amd_initenv();
|
||||
|
||||
} else { /* S3 detect */
|
||||
printk(BIOS_INFO, "S3 detected\n");
|
||||
|
||||
post_code(0x60);
|
||||
agesawrapper_amdinitresume();
|
||||
|
||||
agesawrapper_amds3laterestore();
|
||||
|
||||
post_code(0x61);
|
||||
prepare_for_resume();
|
||||
}
|
||||
|
||||
post_code(0x50);
|
||||
copy_and_run();
|
||||
printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
|
||||
|
||||
post_code(0x54); /* Should never see this post code. */
|
||||
}
|
Loading…
Reference in New Issue