mb/system76/lemp9: enable TPM
L140CU has a TPM2 connected via SPI. Add the TPM device to the devicetree and enable it. According to Intel doc#615170-001, PIRQ is required for SPI TPM to work. Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as TPM interrupt in Kconfig. Note: The PCH maps either LPC TPM or SPI TPM to the same address and handles either LPC or SPI communication transparently. Thus we can use MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address. Tested, but only polling works currently, because there is some upstream issue with the tpm_tis module in current Linux kernels. [1] [1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -10,9 +10,8 @@ config BOARD_SPECIFIC_OPTIONS
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select GENERIC_SPD_BIN
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select GENERIC_SPD_BIN
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select INTEL_GMA_HAVE_VBT
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select INTEL_LPSS_UART_FOR_CONSOLE
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# Chip select 2 is not yet supported by intel fast_spi
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select MAINBOARD_HAS_LPC_TPM
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# select MAINBOARD_HAS_SPI_TPM_CR50
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select MAINBOARD_HAS_TPM2
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# select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select NO_UART_ON_SUPERIO
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select SOC_INTEL_COMETLAKE
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select SOC_INTEL_COMETLAKE
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA
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@ -77,17 +76,12 @@ config VGA_BIOS_ID
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string
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string
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default "8086,9b41"
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default "8086,9b41"
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config TPM_PIRQ
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hex
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default 0x10 # GPP_A7/PIRQA#
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config POST_DEVICE
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config POST_DEVICE
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bool
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bool
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default n
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default n
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# Chip select 2 is not yet supported by intel fast_spi
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#config DRIVER_TPM_SPI_BUS
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# hex
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# default 0x0
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#
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#config DRIVER_TPM_SPI_CHIP
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# int
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# default 2
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endif
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endif
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@ -238,12 +238,16 @@ chip soc/intel/cannonlake
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device pci 1e.1 off end # UART #1
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on end # LPC Interface
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device pci 1f.0 on # LPC Interface
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chip drivers/pc80/tpm # TPM
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 off end # P2SB
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device pci 1f.1 off end # P2SB
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device pci 1f.2 off end # Power Management Controller
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device pci 1f.2 off end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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device pci 1f.6 off end # GbE
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end
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end
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end
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end
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@ -76,8 +76,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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// GSPI0
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// GSPI0
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// TODO - TPM_PIRQ#
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// PIRQA# / TPM_PIRQ#
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PAD_CFG_NC(GPP_A7),
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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// LPC
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// LPC
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// PM_CLKRUN# with pull-up
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// PM_CLKRUN# with pull-up
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