skylake: Prepare GPE for use in bootblock
Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17135 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -301,6 +301,9 @@ void pch_early_init(void)
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/* Program SMBUS_BASE_ADDRESS and Enable it */
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enable_smbus();
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/* Set up GPE configuration */
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pmc_gpe_init();
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soc_config_rtc();
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enable_heci();
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@ -23,7 +23,7 @@
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#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if ENV_RAMSTAGE
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#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#include <device/pci_def.h>
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#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
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@ -186,6 +186,9 @@ uint16_t smbus_tco_regs(void);
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/* Set the DISB after DRAM init */
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void pmc_set_disb(void);
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/* Initialize GPEs */
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void pmc_gpe_init(void);
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static inline int deep_s3_enabled(void)
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{
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uint32_t deep_s3_pol;
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@ -129,42 +129,6 @@ static void pch_rtc_init(void)
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cmos_init(rtc_failed);
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}
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static void pmc_gpe_init(config_t *config)
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{
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uint8_t *pmc_regs;
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uint32_t gpio_cfg;
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uint32_t gpio_cfg_reg;
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const uint32_t gpio_cfg_mask =
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(GPE0_DWX_MASK << GPE0_DW0_SHIFT) |
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(GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
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(GPE0_DWX_MASK << GPE0_DW2_SHIFT);
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pmc_regs = pmc_mmio_regs();
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gpio_cfg = 0;
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/* Route the GPIOs to the GPE0 block. Determine that all values
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* are different, and if they aren't use the reset values. */
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if (config->gpe0_dw0 == config->gpe0_dw1 ||
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config->gpe0_dw1 == config->gpe0_dw2) {
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printk(BIOS_INFO, "PMC: Using default GPE route.\n");
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gpio_cfg = read32(pmc_regs + GPIO_CFG);
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} else {
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gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT;
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gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT;
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gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT;
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}
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gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask;
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gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
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write32(pmc_regs + GPIO_CFG, gpio_cfg_reg);
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/* Set the routes in the GPIO communities as well. */
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gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT);
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/* Set GPE enables based on devictree. */
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enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
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config->gpe0_en_3, config->gpe0_en_4);
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}
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static void pch_power_options(void)
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{
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u16 reg16;
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@ -172,7 +136,6 @@ static void pch_power_options(void)
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/*PMC Controller Device 0x1F, Func 02*/
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device_t dev = PCH_DEV_PMC;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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/*
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@ -207,7 +170,7 @@ static void pch_power_options(void)
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printk(BIOS_INFO, "Set power %s after power failure.\n", state);
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/* Set up GPE configuration. */
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pmc_gpe_init(config);
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pmc_gpe_init();
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}
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static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
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@ -19,6 +19,8 @@
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* and the differences between PCH variants.
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*/
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#define __SIMPLE_DEVICE__
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -27,6 +29,7 @@
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#include <halt.h>
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#include <rules.h>
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#include <stdlib.h>
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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@ -34,6 +37,7 @@
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#include <soc/pm.h>
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#include <soc/pmc.h>
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#include <soc/smbus.h>
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#include "chip.h"
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/* Print status bits with descriptive names */
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static void print_status_bits(u32 status, const char *bit_names[])
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@ -465,3 +469,47 @@ void poweroff(void)
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if (!ENV_SMM)
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halt();
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}
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void pmc_gpe_init(void)
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{
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ROMSTAGE_CONST struct soc_intel_skylake_config *config;
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ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
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uint8_t *pmc_regs;
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uint32_t gpio_cfg;
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uint32_t gpio_cfg_reg;
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const uint32_t gpio_cfg_mask =
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(GPE0_DWX_MASK << GPE0_DW0_SHIFT) |
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(GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
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(GPE0_DWX_MASK << GPE0_DW2_SHIFT);
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/* Look up the device in devicetree */
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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return;
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}
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config = dev->chip_info;
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pmc_regs = pmc_mmio_regs();
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/* Route the GPIOs to the GPE0 block. Determine that all values
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* are different, and if they aren't use the reset values. */
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gpio_cfg = 0;
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if (config->gpe0_dw0 == config->gpe0_dw1 ||
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config->gpe0_dw1 == config->gpe0_dw2) {
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printk(BIOS_INFO, "PMC: Using default GPE route.\n");
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gpio_cfg = read32(pmc_regs + GPIO_CFG);
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} else {
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gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT;
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gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT;
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gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT;
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}
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gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask;
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gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
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write32(pmc_regs + GPIO_CFG, gpio_cfg_reg);
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/* Set the routes in the GPIO communities as well. */
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gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT);
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/* Set GPE enables based on devictree. */
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enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
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config->gpe0_en_3, config->gpe0_en_4);
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}
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