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mb/google/octopus/variants/baseboard: Update DPTF parameters 

This patch updates DPTF parameters for Octopus baseboard.

BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I1456b7b9ee9e02491c66b0709c710e1a7ec08cc5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Sumeet Pawnikar 2018-06-07 11:43:24 +05:30 committed by Patrick Georgi
parent 510758826d
commit f0c50b0e4b
2 changed files with 10 additions and 10 deletions
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6
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
View File

@ -42,10 +42,10 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_N_63_32"
# PL1 override 8000 mW: Due to error in the energy calculation for
# PL1 override 12000 mW: Due to error in the energy calculation for
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 8W.
register "tdp_pl1_override_mw" = "8000"
# be reached when RAPL PL1 is set to 12W.
register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
register "tdp_pl2_override_mw" = "15000"

14
src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl
View File

@ -14,8 +14,8 @@
*/
/* Below values might change after Thermal Tuning. */
#define DPTF_CPU_PASSIVE 95
#define DPTF_CPU_CRITICAL 105
#define DPTF_CPU_PASSIVE 90
#define DPTF_CPU_CRITICAL 99
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "Battery"
@ -24,12 +24,12 @@
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "Ambient"
#define DPTF_TSR1_PASSIVE 46
#define DPTF_TSR1_CRITICAL 75
#define DPTF_TSR1_PASSIVE 48
#define DPTF_TSR1_CRITICAL 90
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "Charger"
#define DPTF_TSR2_PASSIVE 58
#define DPTF_TSR2_PASSIVE 62
#define DPTF_TSR2_CRITICAL 90
#define DPTF_ENABLE_CHARGER
@ -48,7 +48,7 @@ Name (DTRT, Package () {
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 0 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
#ifdef DPTF_ENABLE_CHARGER
/* Charger Effect on Temp Sensor 2 */
@ -65,7 +65,7 @@ Name (MPPC, Package ()
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
3000, /* PowerLimitMinimum */
8000, /* PowerLimitMaximum */
12000, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */
200 /* StepSize */