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util/inteltool: add missing native functions of special pads for CNL-LP 

Add the missing native functions for special gpio pads for CNL-LP,
which are documented in the PCH EDS and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-09-09 19:55:36 +02:00
parent b0630464d9
commit f0c5d87a0e
1 changed files with 26 additions and 26 deletions
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52
util/inteltool/gpio_names/cannonlake_lp.h
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@ -75,36 +75,36 @@ const struct gpio_group cannonlake_pch_lp_group_b = {
};
const char *const cannonlake_pch_lp_group_c_names[] = {
"GPP_C0", "SMBCLK", "n/a",
"GPP_C1", "SMBDATA", "n/a",
"GPP_C2", "SMBALERT#", "n/a",
"GPP_C3", "SML0CLK", "n/a",
"GPP_C4", "SML0DATA", "n/a",
"GPP_C5", "SML0ALERT#", "n/a",
"GPP_C6", "SML1CLK", "n/a",
"GPP_C7", "SML1DATA", "n/a",
"GPP_C8", "UART0_RXD", "n/a",
"GPP_C9", "UART0_TXD", "n/a",
"GPP_C10", "UART0_RTS#", "n/a",
"GPP_C11", "UART0_CTS#", "n/a",
"GPP_C12", "UART1_RXD", "ISH_UART1_RXD",
"GPP_C13", "UART1_TXD", "ISH_UART1_TXD",
"GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#",
"GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#",
"GPP_C16", "I2C0_SDA", "n/a",
"GPP_C17", "I2C0_SCL", "n/a",
"GPP_C18", "I2C1_SDA", "n/a",
"GPP_C19", "I2C1_SCL", "n/a",
"GPP_C20", "UART2_RXD", "n/a",
"GPP_C21", "UART2_TXD", "n/a",
"GPP_C22", "UART2_RTS#", "n/a",
"GPP_C23", "UART2_CTS#", "n/a",
"GPP_C0", "SMBCLK", "n/a", "n/a",
"GPP_C1", "SMBDATA", "n/a", "n/a",
"GPP_C2", "SMBALERT#", "n/a", "n/a",
"GPP_C3", "SML0CLK", "n/a", "n/a",
"GPP_C4", "SML0DATA", "n/a", "n/a",
"GPP_C5", "SML0ALERT#", "n/a", "n/a",
"GPP_C6", "SML1CLK", "n/a", "n/a",
"GPP_C7", "SML1DATA", "n/a", "n/a",
"GPP_C8", "UART0_RXD", "n/a", "n/a",
"GPP_C9", "UART0_TXD", "n/a", "n/a",
"GPP_C10", "UART0_RTS#", "n/a", "n/a",
"GPP_C11", "UART0_CTS#", "n/a", "n/a",
"GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "CNV_MFUART1_RXD",
"GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "CNV_MFUART1_TXD",
"GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "CNV_MFUART1_RTS",
"GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "CNV_MFUART1_CTS",
"GPP_C16", "I2C0_SDA", "n/a", "n/a",
"GPP_C17", "I2C0_SCL", "n/a", "n/a",
"GPP_C18", "I2C1_SDA", "n/a", "n/a",
"GPP_C19", "I2C1_SCL", "n/a", "n/a",
"GPP_C20", "UART2_RXD", "n/a", "n/a",
"GPP_C21", "UART2_TXD", "n/a", "n/a",
"GPP_C22", "UART2_RTS#", "n/a", "n/a",
"GPP_C23", "UART2_CTS#", "n/a", "n/a",
};
const struct gpio_group cannonlake_pch_lp_group_c = {
.display = "------- GPIO Group GPP_C -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3,
.func_count = 3,
.pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 4,
.func_count = 4,
.pad_names = cannonlake_pch_lp_group_c_names,
};