riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with featurei suffixd charactersa, it also comes with feature_ful suffix_ed words_mith. Much creative, very appreciate. To accommodate for this madness, enable the already existing (but off by default) support for that in our gcc11 build, support using by detecting the compiler's behavior in xcompile and pass that knowledge along to our build system. Then cross our fingers and hope for the best! Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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@ -21,19 +21,25 @@ $(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32")
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endif
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endif
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# Needed for -print-libgcc-file-name which gets confused about all those arch
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# suffixes in ARCH_SUFFIX_riscv.
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simple_riscv_flags = $(riscv_flags)
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ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
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riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
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riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
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simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
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else
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riscv_flags += $(_rv_flags)
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simple_riscv_flags += $(_rv_flags)
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endif
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riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
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riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI)
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COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(simple_riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_romstage = $(shell $(GCC_romstage) $(simple_riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(simple_riscv_flags) -print-libgcc-file-name)
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################################################################################
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## bootblock
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@ -681,11 +681,13 @@ build_BINUTILS() {
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if [ $TARGETARCH = "x86_64-elf" ]; then
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ADDITIONALTARGET=",i386-elf"
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fi
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# shellcheck disable=SC2086
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CC="$(hostcc target)" CXX="$(hostcxx target)" \
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../binutils-${BINUTILS_VERSION}/configure --prefix="$TARGETDIR" \
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--target=${TARGETARCH} --enable-targets=${TARGETARCH}${ADDITIONALTARGET} \
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--disable-werror --disable-nls --enable-lto \
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--enable-gold --enable-multilib \
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${BINUTILS_OPTIONS} \
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CFLAGS="$HOSTCFLAGS" \
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CXXFLAGS="$HOSTCFLAGS" \
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|| touch .failed
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@ -932,7 +934,9 @@ case "$TARGETARCH" in
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x86_64*) TARGETARCH=x86_64-elf;;
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i386-elf) ;;
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i386-mingw32) ;;
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riscv-elf) TARGETARCH=riscv64-elf;;
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riscv-elf) TARGETARCH=riscv64-elf
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GCC_OPTIONS="$GCC_OPTIONS --with-isa-spec=20191213"
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BINUTILS_OPTIONS="$BINUTILS_OPTIONS --with-isa-spec=20191213";;
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powerpc64*-linux*) ;;
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i386*) TARGETARCH=i386-elf;;
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arm*) TARGETARCH=arm-eabi;;
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@ -202,6 +202,10 @@ detect_special_flags() {
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"$LDFLAGS --fix-cortex-a53-843419" && \
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LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419"
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;;
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riscv)
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testcc "$GCC" "$FLAGS_GCC -march=rv64iadc_zicsr_zifencei" &&
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ARCH_SUFFIX="_zicsr_zifencei"
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;;
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esac
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}
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@ -221,6 +225,7 @@ report_arch_toolchain() {
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# elf${TWIDTH}-${TBFDARCH} toolchain (${GCC})
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ARCH_SUPPORTED+=${TARCH}
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SUBARCH_SUPPORTED+=${TSUPP-${TARCH}}
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ARCH_SUFFIX_${TARCH}:=${ARCH_SUFFIX}
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# GCC
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GCC_CC_${TARCH}:=${GCC}
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@ -399,6 +404,7 @@ test_architecture() {
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unset TABI TARCH TBFDARCH TCLIST TENDIAN TSUPP TWIDTH
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unset CC_RT_EXTRA_GCC CC_RT_EXTRA_CLANG
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unset GCC CLANG
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unset ARCH_SUFFIX
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if type "arch_config_$architecture" > /dev/null; then
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"arch_config_$architecture"
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else
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