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mb/google/volteer/var/voema: Enable RTD3 for the NVMe device 

Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.

Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.

BUG=b:169356808
TEST=tested on voema

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu 2020-12-22 13:42:39 +08:00 committed by Hung-Te Lin
parent 749a78d179
commit f0df12dd17
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/google/volteer/variants/voema/overridetree.cb
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@ -81,6 +81,14 @@ chip soc/intel/tigerlake
device pnp 0c09.0 on end device pnp 0c09.0 on end
end end
end end
device ref pcie_rp9 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "0"
device generic 0 on end
end
end
device ref pmc hidden device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the # The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy. # PMC.MUX device in the ACPI hierarchy.