soc/intel/cannonlake: Fill the SMI usage
Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao
Aaron Durbin
parent
a515849259
commit
f0eb99996d
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@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_HARD_RESET
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select HAVE_INTEL_FIRMWARE
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select IOAPIC
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@ -31,7 +32,9 @@ config CPU_SPECIFIC_OPTIONS
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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select REG_SCRIPT
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select SMM_TSEG
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select SMP
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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@ -58,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
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select SOC_INTEL_COMMON_RESET
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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@ -5,6 +5,7 @@ subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/bootblock.c
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@ -37,12 +38,20 @@ ramstage-y += memmap.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c
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ramstage-y += vr_config.c
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smm-y += gpio.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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smm-$(CONFIG_UART_DEBUG) += uart.c
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smm-$(CONFIG_UART_DEBUG) += uart_pch.c
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postcar-y += memmap.c
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postcar-y += pmutil.c
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postcar-y += spi.c
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@ -21,10 +21,12 @@
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#include <cpu/intel/turbo.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/smm.h>
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#include <romstage_handoff.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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static void soc_fsp_load(void)
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{
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@ -197,13 +199,27 @@ void soc_core_init(device_t cpu)
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/* Enable Turbo */
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enable_turbo();
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}
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static void per_cpu_smm_trigger(void)
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{
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/* Relocate the SMM handler. */
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smm_relocate();
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}
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static void post_mp_init(void)
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{
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/* Set Max Ratio */
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cpu_set_max_ratio();
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/*
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* Now that all APs have been relocated as well as the BSP let SMIs
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* start flowing.
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*/
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smm_southbridge_enable();
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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static const struct mp_ops mp_ops = {
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@ -214,7 +230,11 @@ static const struct mp_ops mp_ops = {
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*/
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.pre_mp_init = soc_fsp_load,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = smm_info,
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.get_microcode_info = get_microcode_info,
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.pre_mp_smm_init = smm_initialize,
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.per_cpu_smm_trigger = per_cpu_smm_trigger,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = post_mp_init,
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};
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@ -20,22 +20,13 @@
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#include <intelblocks/msr.h>
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_BIOS_UPGD_TRIG 0x7a
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#define IA32_THERM_INTERRUPT 0x19b
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#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
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#define ENERGY_POLICY_PERFORMANCE 0
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define PRMRR_PHYS_BASE_MSR 0x1f4
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#define IA32_PLATFORM_DCA_CAP 0x1f8
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define MSR_SGX_OWNEREPOCH0 0x300
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#define MSR_SGX_OWNEREPOCH1 0x301
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define IA32_PLATFORM_DCA_CAP 0x1f9
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#define MSR_VR_MISC_CONFIG2 0x636
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#define MSR_PP0_POWER_LIMIT 0x638
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#define MSR_PP1_POWER_LIMIT 0x640
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#endif
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@ -0,0 +1,71 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_SMM_H_
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#define _SOC_SMM_H_
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <fsp/memmap.h>
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#include <soc/gpio.h>
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struct ied_header {
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char signature[10];
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u32 size;
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u8 reserved[34];
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} __packed;
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struct smm_relocation_params {
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u32 smram_base;
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u32 smram_size;
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u32 ied_base;
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u32 ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t emrr_base;
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msr_t emrr_mask;
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msr_t uncore_emrr_base;
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msr_t uncore_emrr_mask;
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/*
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* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE
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*/
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int smm_save_state_in_msrs;
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};
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/* Mainboard handler for eSPI SMIs */
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void mainboard_smi_espi_handler(void);
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase);
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void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size);
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void smm_initialize(void);
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void smm_relocate(void);
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#else /* CONFIG_HAVE_SMI_HANDLER */
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static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase) {}
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static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size) {}
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static inline void smm_initialize(void) {}
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static inline void smm_relocate(void) {}
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#endif /* CONFIG_HAVE_SMI_HANDLER */
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#endif
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@ -23,9 +23,64 @@
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#include <intelblocks/systemagent.h>
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#include <soc/bootblock.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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void smm_region(void **start, size_t *size)
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{
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*start = (void *)sa_get_tseg_base();
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*size = sa_get_tseg_size();
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}
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/*
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* Subregions within SMM
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* +-------------------------+ BGSM
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* | IED | IED_REGION_SIZE
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* +-------------------------+
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* | External Stage Cache | SMM_RESERVED_SIZE
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* +-------------------------+
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* | code and data |
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* | (TSEG) |
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* +-------------------------+ TSEG
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*/
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int smm_subregion(int sub, void **start, size_t *size)
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{
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uintptr_t sub_base;
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size_t sub_size;
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void *smm_base;
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const size_t ied_size = CONFIG_IED_REGION_SIZE;
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const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
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smm_region(&smm_base, &sub_size);
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sub_base = (uintptr_t)smm_base;
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switch (sub) {
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case SMM_SUBREGION_HANDLER:
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/* Handler starts at the base of TSEG. */
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sub_size -= ied_size;
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sub_size -= cache_size;
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break;
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case SMM_SUBREGION_CACHE:
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/* External cache is in the middle of TSEG. */
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sub_base += sub_size - (ied_size + cache_size);
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sub_size = cache_size;
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break;
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case SMM_SUBREGION_CHIPSET:
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/* IED is at the top. */
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sub_base += sub_size - ied_size;
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sub_size = ied_size;
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break;
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default:
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return -1;
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}
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*start = (void *)sub_base;
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*size = sub_size;
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return 0;
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}
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static void *top_of_ram_register(void)
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{
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int num;
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@ -16,8 +16,14 @@
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*/
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#include <intelblocks/smihandler.h>
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#include <soc/pm.h>
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static smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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[PM1_STS_BIT] = smihandler_southbridge_pm1,
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@ -0,0 +1,310 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <intelblocks/smm.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase,
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struct smm_relocation_params *relo_params)
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{
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u32 smbase;
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u32 iedbase;
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/*
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* The relocated handler runs with all CPUs concurrently. Therefore
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* stagger the entry points adjusting SMBASE downwards by save state
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* size * CPU num.
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*/
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smbase = staggered_smbase;
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iedbase = relo_params->ied_base;
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
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smbase, iedbase);
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/*
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* All threads need to set IEDBASE and SMBASE to the relocated
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* handler region. However, the save state location depends on the
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* smm_save_state_in_msrs field in the relocation parameters. If
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* smm_save_state_in_msrs is non-zero then the CPUs are relocating
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* the SMM handler in parallel, and each CPUs save state area is
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* located in their respective MSR space. If smm_save_state_in_msrs
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* is zero then the SMM relocation is happening serially so the
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* save state is at the same default location for all CPUs.
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*/
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if (relo_params->smm_save_state_in_msrs) {
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msr_t smbase_msr;
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msr_t iedbase_msr;
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smbase_msr.lo = smbase;
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smbase_msr.hi = 0;
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/*
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* According the BWG the IEDBASE MSR is in bits 63:32. It's
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* not clear why it differs from the SMBASE MSR.
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*/
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iedbase_msr.lo = 0;
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iedbase_msr.hi = iedbase;
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wrmsr(SMBASE_MSR, smbase_msr);
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wrmsr(IEDBASE_MSR, iedbase_msr);
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} else {
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em64t101_smm_state_save_area_t *save_state;
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save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
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sizeof(*save_state));
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save_state->smbase = smbase;
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save_state->iedbase = iedbase;
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}
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}
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/* Returns 1 if SMM MSR save state was set. */
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static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
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{
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msr_t smm_mca_cap;
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smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
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if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
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msr_t smm_feature_control;
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smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
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smm_feature_control.hi = 0;
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smm_feature_control.lo |= SMM_CPU_SAVE_EN;
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wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
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relo_params->smm_save_state_in_msrs = 1;
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}
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return relo_params->smm_save_state_in_msrs;
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}
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/*
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* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here.
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*/
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params = &smm_reloc_params;
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printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
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/*
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* Determine if the processor supports saving state in MSRs. If so,
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* enable it before the non-BSPs run so that SMM relocation can occur
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* in parallel in the non-BSP CPUs.
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*/
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if (cpu == 0) {
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/*
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* If smm_save_state_in_msrs is 1 then that means this is the
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* 2nd time through the relocation handler for the BSP.
|
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* Parallel SMM handler relocation is taking place. However,
|
||||
* it is desired to access other CPUs save state in the real
|
||||
* SMM handler. Therefore, disable the SMM save state in MSRs
|
||||
* feature.
|
||||
*/
|
||||
if (relo_params->smm_save_state_in_msrs) {
|
||||
msr_t smm_feature_control;
|
||||
|
||||
smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
|
||||
smm_feature_control.lo &= ~SMM_CPU_SAVE_EN;
|
||||
wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
|
||||
} else if (bsp_setup_msr_save_state(relo_params))
|
||||
/*
|
||||
* Just return from relocation handler if MSR save
|
||||
* state is enabled. In that case the BSP will come
|
||||
* back into the relocation handler to setup the new
|
||||
* SMBASE as well disabling SMM save state in MSRs.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
/* Make appropriate changes to the save state map. */
|
||||
update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
|
||||
|
||||
/* Write EMRR and SMRR MSRs based on indicated support. */
|
||||
mtrr_cap = rdmsr(MTRR_CAP_MSR);
|
||||
if (mtrr_cap.lo & SMRR_SUPPORTED)
|
||||
write_smrr(relo_params);
|
||||
}
|
||||
|
||||
static void fill_in_relocation_params(device_t dev,
|
||||
struct smm_relocation_params *params)
|
||||
{
|
||||
void *handler_base;
|
||||
size_t handler_size;
|
||||
void *ied_base;
|
||||
size_t ied_size;
|
||||
void *tseg_base;
|
||||
size_t tseg_size;
|
||||
u32 emrr_base;
|
||||
u32 emrr_size;
|
||||
int phys_bits;
|
||||
/* All range registers are aligned to 4KiB */
|
||||
const u32 rmask = ~(4 * KiB - 1);
|
||||
|
||||
/*
|
||||
* Some of the range registers are dependent on the number of physical
|
||||
* address bits supported.
|
||||
*/
|
||||
phys_bits = cpu_phys_address_size();
|
||||
|
||||
smm_region(&tseg_base, &tseg_size);
|
||||
smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
|
||||
smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
|
||||
|
||||
params->smram_size = handler_size;
|
||||
params->smram_base = (uintptr_t)handler_base;
|
||||
|
||||
params->ied_base = (uintptr_t)ied_base;
|
||||
params->ied_size = ied_size;
|
||||
|
||||
/* SMRR has 32-bits of valid address aligned to 4KiB. */
|
||||
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
|
||||
params->smrr_base.hi = 0;
|
||||
params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
|
||||
| MTRR_PHYS_MASK_VALID;
|
||||
params->smrr_mask.hi = 0;
|
||||
|
||||
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
|
||||
emrr_base = (params->ied_base + 2 * MiB) & rmask;
|
||||
emrr_size = params->ied_size - 2 * MiB;
|
||||
|
||||
/*
|
||||
* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
|
||||
* on the number of physical address bits supported.
|
||||
*/
|
||||
params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
|
||||
params->emrr_base.hi = 0;
|
||||
params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
|
||||
| MTRR_PHYS_MASK_VALID;
|
||||
params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
|
||||
|
||||
/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
|
||||
params->uncore_emrr_base.lo = emrr_base;
|
||||
params->uncore_emrr_base.hi = 0;
|
||||
params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
|
||||
MTRR_PHYS_MASK_VALID;
|
||||
params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
|
||||
}
|
||||
|
||||
static void setup_ied_area(struct smm_relocation_params *params)
|
||||
{
|
||||
char *ied_base;
|
||||
|
||||
struct ied_header ied = {
|
||||
.signature = "INTEL RSVD",
|
||||
.size = params->ied_size,
|
||||
.reserved = {0},
|
||||
};
|
||||
|
||||
ied_base = (void *)params->ied_base;
|
||||
|
||||
printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
|
||||
printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
|
||||
|
||||
/* Place IED header at IEDBASE. */
|
||||
memcpy(ied_base, &ied, sizeof(ied));
|
||||
|
||||
/* Zero out 32KiB at IEDBASE + 1MiB */
|
||||
memset(ied_base + 1 * MiB, 0, 32 * KiB);
|
||||
}
|
||||
|
||||
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
|
||||
size_t *smm_save_state_size)
|
||||
{
|
||||
device_t dev = SA_DEV_ROOT;
|
||||
|
||||
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
|
||||
|
||||
fill_in_relocation_params(dev, &smm_reloc_params);
|
||||
|
||||
if (smm_reloc_params.ied_size)
|
||||
setup_ied_area(&smm_reloc_params);
|
||||
|
||||
*perm_smbase = smm_reloc_params.smram_base;
|
||||
*perm_smsize = smm_reloc_params.smram_size;
|
||||
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
|
||||
}
|
||||
|
||||
void smm_initialize(void)
|
||||
{
|
||||
/* Clear the SMM state in the southbridge. */
|
||||
smm_southbridge_clear_state();
|
||||
|
||||
/*
|
||||
* Run the relocation handler for on the BSP to check and set up
|
||||
* parallel SMM relocation.
|
||||
*/
|
||||
smm_initiate_relocation();
|
||||
|
||||
if (smm_reloc_params.smm_save_state_in_msrs)
|
||||
printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
|
||||
}
|
||||
|
||||
void smm_relocate(void)
|
||||
{
|
||||
/*
|
||||
* If smm_save_state_in_msrs is non-zero then parallel SMM relocation
|
||||
* shall take place. Run the relocation handler a second time on the
|
||||
* BSP to do * the final move. For APs, a relocation handler always
|
||||
* needs to be run.
|
||||
*/
|
||||
if (smm_reloc_params.smm_save_state_in_msrs)
|
||||
smm_initiate_relocation_parallel();
|
||||
else if (!boot_cpu())
|
||||
smm_initiate_relocation();
|
||||
}
|
||||
|
||||
void smm_lock(void)
|
||||
{
|
||||
/*
|
||||
* LOCK the SMM memory window and enable normal SMM.
|
||||
* After running this function, only a full reset can
|
||||
* make the SMM registers writable again.
|
||||
*/
|
||||
printk(BIOS_DEBUG, "Locking SMM.\n");
|
||||
pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
|
||||
}
|
||||
|
|
@ -92,6 +92,21 @@ void smihandler_southbridge_pm1(
|
|||
void smihandler_southbridge_gpe0(
|
||||
const struct smm_save_state_ops *save_state_ops);
|
||||
|
||||
/*
|
||||
* This function should be implemented in SOC specific code to handle
|
||||
* MC event. The default functionality is provided in
|
||||
* soc/intel/common/block/smm/smihandler.c
|
||||
*/
|
||||
void smihandler_southbridge_mc(
|
||||
const struct smm_save_state_ops *save_state_ops);
|
||||
|
||||
/*
|
||||
* This function should be implemented in SOC specific code to handle
|
||||
* minitor event. The default functionality is provided in
|
||||
* soc/intel/common/block/smm/smihandler.c
|
||||
*/
|
||||
void smihandler_southbridge_monitor(
|
||||
const struct smm_save_state_ops *save_state_ops);
|
||||
/*
|
||||
* This function should be implemented in SOC specific code to handle
|
||||
* SMI_TCO event. The default functionality is provided in
|
||||
|
|
|
|||
|
|
@ -75,6 +75,8 @@ void smihandler_southbridge_monitor(
|
|||
u32 data, mask = 0;
|
||||
u8 trap_sts;
|
||||
int i;
|
||||
global_nvs_t *gnvs = smm_get_gnvs();
|
||||
|
||||
/* TRSR - Trap Status Register */
|
||||
trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST);
|
||||
/* Clear trap(s) in TRSR */
|
||||
|
|
|
|||
Loading…
Reference in New Issue