mainboard/msi/ms7d25: Enable PTT
Original firmware ships with PTT enabled by default on poweron. PTT takes priority over SPI/LPC TPM so enable the CRB interface until coreboot implements a way to select the interface and adapt the API to handle any TPM detection. TEST=Boot the board and see PTT is detected by Windows and Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -15,3 +15,5 @@ CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
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CONFIG_TIANOCORE_CBMEM_LOGGING=y
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CONFIG_TIANOCORE_CBMEM_LOGGING=y
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CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
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CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
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CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
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CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
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CONFIG_TPM2=y
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CONFIG_TPM_MEASURED_BOOT=y
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@ -11,6 +11,8 @@ config BOARD_MSI_MS7D25
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select INTEL_GMA_HAVE_VBT
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select CRB_TPM
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select HAVE_INTEL_PTT
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if BOARD_MSI_MS7D25
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if BOARD_MSI_MS7D25
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@ -225,5 +225,9 @@ chip soc/intel/alderlake
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register "pch_hda_idisp_codec_enable" = "true"
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register "pch_hda_idisp_codec_enable" = "true"
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end
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end
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device ref smbus on end
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device ref smbus on end
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chip drivers/crb
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device mmio 0xfed40000 on end
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end
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end
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end
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end
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end
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