mainboard/msi/ms7d25: Enable PTT

Original firmware ships with PTT enabled by default on poweron.
PTT takes priority over SPI/LPC TPM so enable the CRB interface
until coreboot implements a way to select the interface and adapt
the API to handle any TPM detection.

TEST=Boot the board and see PTT is detected by Windows and Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2022-04-23 00:22:20 +02:00
parent ed8216d42d
commit f0f8a5fda8
3 changed files with 8 additions and 0 deletions

View File

@ -15,3 +15,5 @@ CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
CONFIG_TIANOCORE_CBMEM_LOGGING=y CONFIG_TIANOCORE_CBMEM_LOGGING=y
CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000 CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
CONFIG_TPM2=y
CONFIG_TPM_MEASURED_BOOT=y

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@ -11,6 +11,8 @@ config BOARD_MSI_MS7D25
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT select INTEL_GMA_HAVE_VBT
select CRB_TPM
select HAVE_INTEL_PTT
if BOARD_MSI_MS7D25 if BOARD_MSI_MS7D25

View File

@ -225,5 +225,9 @@ chip soc/intel/alderlake
register "pch_hda_idisp_codec_enable" = "true" register "pch_hda_idisp_codec_enable" = "true"
end end
device ref smbus on end device ref smbus on end
chip drivers/crb
device mmio 0xfed40000 on end
end
end end
end end