mainboard/kontron: Use C89 comments style & remove commented code
Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16908 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
Martin Roth
parent
8d94fbd999
commit
f10b5ff8a9
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@ -29,22 +29,22 @@ static const struct irq_routing_table intel_irq_routing_table = {
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0xf, /* u8 checksum. */
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
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{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
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{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
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{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
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{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
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{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
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{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
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{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
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{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
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{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
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{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
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{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
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{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
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{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
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{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
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{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
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{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
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{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
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{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
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{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
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{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
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{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
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{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
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{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
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{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
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{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
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{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
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{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
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}
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@ -41,15 +41,15 @@ static void hwm_bank(u8 bank)
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#define FAN_CRUISE_CONTROL_THERMAL 2
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#define FAN_SPEED_5625 0
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//#define FAN_TEMPERATURE_30DEGC 0
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struct fan_speed {
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u8 fan_in;
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u16 fan_speed;
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};
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// FANIN Target Speed Register
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// FANIN = 337500 / RPM
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/* FANIN Target Speed Register */
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/* FANIN = 337500 / RPM */
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struct fan_speed fan_speeds[] = {
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{ 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
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{ 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
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@ -79,34 +79,27 @@ static void hwm_setup(void)
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get_option(&cpufan_control, "cpufan_cruise_control");
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cpufan_speed = FAN_SPEED_5625;
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get_option(&cpufan_speed, "cpufan_speed");
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//cpufan_temperature = FAN_TEMPERATURE_30DEGC;
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//get_option(&cpufan_temperature, "cpufan_temperature");
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sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
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get_option(&sysfan_control, "sysfan_cruise_control");
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sysfan_speed = FAN_SPEED_5625;
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get_option(&sysfan_speed, "sysfan_speed");
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//sysfan_temperature = FAN_TEMPERATURE_30DEGC;
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//get_option(&sysfan_temperature, "sysfan_temperature");
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// hwm_write(0x31, 0x20); // AVCC high limit
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// hwm_write(0x34, 0x06); // VIN2 low limit
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hwm_bank(0);
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hwm_write(0x59, 0x20); // Diode Selection
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hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
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hwm_write(0x59, 0x20); /* Diode Selection */
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hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */
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hwm_bank(4);
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hwm_write(0x54, 0xf1); // SYSTIN temperature offset
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hwm_write(0x55, 0x19); // CPUTIN temperature offset
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hwm_write(0x56, 0xfc); // AUXTIN temperature offset
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hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */
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hwm_write(0x55, 0x19); /* CPUTIN temperature offset */
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hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */
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hwm_bank(0x80); // Default
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hwm_bank(0x80); /* Default */
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u8 fan_config = 0;
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// 00 FANOUT is Manual Mode
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// 01 FANOUT is Thermal Cruise Mode
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// 10 FANOUT is Fan Speed Cruise Mode
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/* 00 FANOUT is Manual Mode */
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/* 01 FANOUT is Thermal Cruise Mode */
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/* 10 FANOUT is Fan Speed Cruise Mode */
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switch (cpufan_control) {
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case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
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case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
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@ -115,20 +108,20 @@ static void hwm_setup(void)
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case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
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case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
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}
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// This register must be written first
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/* This register must be written first */
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hwm_write(0x04, fan_config);
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switch (cpufan_control) {
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case FAN_CRUISE_CONTROL_SPEED:
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printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
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fan_speeds[cpufan_speed].fan_speed);
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hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
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hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */
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break;
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case FAN_CRUISE_CONTROL_THERMAL:
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printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
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temperatures[cpufan_temperature].deg_celsius,
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temperatures[cpufan_temperature].deg_fahrenheit);
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hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
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hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */
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break;
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}
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@ -136,29 +129,27 @@ static void hwm_setup(void)
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case FAN_CRUISE_CONTROL_SPEED:
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printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
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fan_speeds[sysfan_speed].fan_speed);
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hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
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hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */
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break;
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case FAN_CRUISE_CONTROL_THERMAL:
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printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
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temperatures[sysfan_temperature].deg_celsius,
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temperatures[sysfan_temperature].deg_fahrenheit);
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hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
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hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */
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break;
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}
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hwm_write(0x0e, 0x02); // Fan Output Step Down Time
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hwm_write(0x0f, 0x02); // Fan Output Step Up Time
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hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */
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hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */
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hwm_write(0x47, 0xaf); // FAN divisor register
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hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
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hwm_write(0x47, 0xaf); /* FAN divisor register */
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hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */
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hwm_write(0x40, 0x01); // Init, but no SMI#
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hwm_write(0x40, 0x01); /* Init, but no SMI# */
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}
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// mainboard_enable is executed as first thing after
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// enumerate_buses().
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/* mainboard_enable is executed as first thing after */
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/* enumerate_buses(). */
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static void mainboard_enable(device_t dev)
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{
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@ -39,8 +39,8 @@ static void *smp_write_config_table(void *v)
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firewire_bus = firewire->bus->secondary;
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}
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// If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
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// highest bus number on the pci bus.
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/* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */
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/* highest bus number on the pci bus. */
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riser = dev_find_device(0x3388, 0x0021, 0);
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if (!riser)
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riser = dev_find_device(0x3388, 0x0022, 0);
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@ -77,11 +77,11 @@ static void *smp_write_config_table(void *v)
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if (riser) {
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/* Old riser card */
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// riser slot top 5:8.0
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/* riser slot top 5:8.0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
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// riser slot middle 5:9.0
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/* riser slot middle 5:9.0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
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// riser slot bottom 5:a.0
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/* riser slot bottom 5:a.0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
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/* New Riser Card */
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@ -13,7 +13,7 @@
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* GNU General Public License for more details.
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*/
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// __PRE_RAM__ means: use "unsigned" for device, not a struct.
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/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
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#include <stdint.h>
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#include <string.h>
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@ -57,21 +57,21 @@ static void ich7_enable_lpc(void)
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{
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int lpt_en = 0;
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if (read_option(lpt, 0) != 0) {
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lpt_en = 1 << 2; // enable LPT
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lpt_en = 1 << 2; /* enable LPT */
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}
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// Enable Serial IRQ
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/* Enable Serial IRQ */
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
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// Set COM1/COM2 decode range
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/* Set COM1/COM2 decode range */
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
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// Enable COM1/COM2/KBD/SuperIO1+2
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/* Enable COM1/COM2/KBD/SuperIO1+2 */
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en);
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// Enable HWM at 0xa00
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/* Enable HWM at 0xa00 */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
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// COM3 decode
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/* COM3 decode */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
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// COM4 decode
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/* COM4 decode */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
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// io 0x300 decode
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/* io 0x300 decode */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
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}
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@ -101,10 +101,10 @@ static void early_superio_config_w83627thg(void)
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dev = PNP_DEV(0x2e, W83627THG_SP1);
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pnp_enter_func_mode(dev);
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pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
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pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */
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pnp_write_config(dev, 0x29, 0x43); // GPIO settings
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pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
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pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */
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pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */
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dev = PNP_DEV(0x2e, W83627THG_SP1);
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pnp_set_logical_device(dev);
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@ -118,7 +118,6 @@ static void early_superio_config_w83627thg(void)
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
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// pnp_write_config(dev, 0xf1, 4); // IRMODE0
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pnp_set_enable(dev, 1);
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dev = PNP_DEV(0x2e, W83627THG_KBC);
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@ -126,25 +125,24 @@ static void early_superio_config_w83627thg(void)
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
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pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
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// pnp_write_config(dev, 0xf0, 0x82);
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pnp_set_enable(dev, 1);
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dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
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pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */
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pnp_set_enable(dev, 1);
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dev = PNP_DEV(0x2e, W83627THG_GPIO2);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 1); // Just enable it
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pnp_set_enable(dev, 1); /* Just enable it */
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dev = PNP_DEV(0x2e, W83627THG_GPIO3);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
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pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
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pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
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pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */
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pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */
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pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */
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dev = PNP_DEV(0x2e, W83627THG_FDC);
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pnp_set_logical_device(dev);
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@ -166,14 +164,14 @@ static void early_superio_config_w83627thg(void)
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dev = PNP_DEV(0x4e, W83627THG_SP1);
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pnp_enter_func_mode(dev);
|
||||
|
||||
pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
|
||||
pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */
|
||||
pnp_set_enable(dev, 0);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
|
||||
pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
|
||||
pnp_set_enable(dev, 1);
|
||||
|
||||
dev = PNP_DEV(0x4e, W83627THG_SP2);
|
||||
pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
|
||||
pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */
|
||||
pnp_set_enable(dev, 0);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
|
||||
pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
|
||||
|
|
@ -201,8 +199,6 @@ static void rcba_config(void)
|
|||
u32 reg32;
|
||||
|
||||
/* Set up virtual channel 0 */
|
||||
//RCBA32(0x0014) = 0x80000001;
|
||||
//RCBA32(0x001c) = 0x03128010;
|
||||
|
||||
/* Device 1f interrupt pin register */
|
||||
RCBA32(0x3100) = 0x00042210;
|
||||
|
|
@ -267,7 +263,7 @@ static void rcba_config(void)
|
|||
RCBA32(0x3418) = reg32;
|
||||
|
||||
/* Enable PCIe Root Port Clock Gate */
|
||||
// RCBA32(0x341c) = 0x00000001;
|
||||
|
||||
}
|
||||
|
||||
static void early_ich7_init(void)
|
||||
|
|
@ -275,15 +271,15 @@ static void early_ich7_init(void)
|
|||
uint8_t reg8;
|
||||
uint32_t reg32;
|
||||
|
||||
// program secondary mlt XXX byte?
|
||||
/* program secondary mlt XXX byte? */
|
||||
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
|
||||
|
||||
// reset rtc power status
|
||||
/* reset rtc power status */
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
|
||||
reg8 &= ~(1 << 2);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
|
||||
|
||||
// usb transient disconnect
|
||||
/* usb transient disconnect */
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
|
||||
reg8 |= (3 << 0);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
|
||||
|
|
@ -317,7 +313,7 @@ static void early_ich7_init(void)
|
|||
RCBA32(0x3e0e) |= (1 << 7);
|
||||
RCBA32(0x3e4e) |= (1 << 7);
|
||||
|
||||
// next step only on ich7m b0 and later:
|
||||
/* next step only on ich7m b0 and later: */
|
||||
reg32 = RCBA32(0x2034);
|
||||
reg32 &= ~(0x0f << 16);
|
||||
reg32 |= (5 << 16);
|
||||
|
|
|
|||
|
|
@ -18,9 +18,9 @@
|
|||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x11060397, // Codec Vendor / Device ID: Via VT1708S
|
||||
0x11060000, // Subsystem ID
|
||||
0x0000000c, // Number of jacks
|
||||
0x11060397, /* Codec Vendor / Device ID: Via VT1708S */
|
||||
0x11060000, /* Subsystem ID */
|
||||
0x0000000c, /* Number of jacks */
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x11060000 */
|
||||
AZALIA_SUBVENDOR(0x0, 0x11060000),
|
||||
|
|
@ -95,9 +95,9 @@ const u32 cim_verb_data[] = {
|
|||
|
||||
|
||||
/* coreboot specific header */
|
||||
0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
|
||||
0x80860101, // Subsystem ID
|
||||
0x00000004, // Number of jacks
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */
|
||||
0x80860101, /* Subsystem ID */
|
||||
0x00000004, /* Number of jacks */
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
|
||||
AZALIA_SUBVENDOR(0x0, 0x80860101),
|
||||
|
|
|
|||
|
|
@ -159,8 +159,8 @@ static int int15_handler(void)
|
|||
|
||||
|
||||
|
||||
// mainboard_enable is executed as first thing after
|
||||
// enumerate_buses().
|
||||
/* mainboard_enable is executed as first thing after */
|
||||
/* enumerate_buses(). */
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -78,8 +78,8 @@ static void pnp_exit_ext_func_mode(device_t dev)
|
|||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
int lvds_3v = 0; // 0 (5V) or 1 (3V3)
|
||||
int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled
|
||||
int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
|
||||
int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */
|
||||
device_t dev = PNP_DEV(0x2e, 0x9);
|
||||
pnp_enter_ext_func_mode(dev);
|
||||
pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
|
||||
|
|
@ -114,17 +114,19 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
|
|||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.thermalbase = 0xfed08000,
|
||||
.system_type = 0, // 0 Mobile, 1 Desktop/Server
|
||||
.system_type = 0, /* 0 Mobile, 1 Desktop/Server */
|
||||
.tseg_size = CONFIG_SMM_TSEG_SIZE,
|
||||
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
|
||||
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
|
||||
.ec_present = 1,
|
||||
.gbe_enable = 1,
|
||||
.ddr3lv_support = 0,
|
||||
// 0 = leave channel enabled
|
||||
// 1 = disable dimm 0 on channel
|
||||
// 2 = disable dimm 1 on channel
|
||||
// 3 = disable dimm 0+1 on channel
|
||||
/*
|
||||
* 0 = leave channel enabled
|
||||
* 1 = disable dimm 0 on channel
|
||||
* 2 = disable dimm 1 on channel
|
||||
* 3 = disable dimm 0+1 on channel
|
||||
*/
|
||||
.dimm_channel0_disabled = 2,
|
||||
.dimm_channel1_disabled = 2,
|
||||
.max_ddr3_freq = 1600,
|
||||
|
|
|
|||
Loading…
Reference in New Issue