mb/amd/mayan: Add framework for morgana crb mayan
mayan is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. amd/mayan is started as a copy of amd/birman. Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ritul Guru
Martin L Roth
parent
21e0da3128
commit
f123ffe78c
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_AMD_MAYAN_MORGANA
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384 # Mayan actually has a 32MiB ROM
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select EC_ACPI
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select SOC_AMD_COMMON_BLOCK_USE_ESPI
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select AMD_SOC_CONSOLE_UART
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select MAINBOARD_HAS_CHROMEOS
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_L1_SUB_STATE
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select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN
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config FMDFILE
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default "src/mainboard/amd/mayan/chromeos.fmd" if CHROMEOS
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default "src/mainboard/amd/mayan/board.fmd"
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config MAINBOARD_DIR
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default "amd/mayan"
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config MAINBOARD_PART_NUMBER
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default "Mayan_Morgana"
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config DEVICETREE
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default "devicetree_morgana.cb"
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config AMD_FWM_POSITION_INDEX
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int
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default 3 if CHROMEOS
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help
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TODO: might need to be adapted for better placement of files in cbfs
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config MAYAN_HAVE_MCHP_FW
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bool "Have Microchip EC firmware?"
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default n
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config MAYAN_MCHP_SIG_FILE
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string "Microchip EC signature file"
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depends on MAYAN_HAVE_MCHP_FW
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default "3rdparty/blobs/mainboard/amd/mayan/EC_mayan_sig.bin"
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help
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The EC sig blob is the first 4kBytes of the firmware image.
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The first 4 bytes form a pointer (with CRC) to where the EC firmware
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is located
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config MAYAN_MCHP_FW_FILE
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string "Microchip EC firmware file"
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depends on MAYAN_HAVE_MCHP_FW
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default "3rdparty/blobs/mainboard/amd/mayan/EC_mayan.bin"
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help
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The EC firmware blob is at the MAYAN_MCHP_FW_OFFSET offset of the
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firmware image.
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config MAYAN_MCHP_FW_OFFSET
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hex
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depends on MAYAN_HAVE_MCHP_FW
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default 0xB80000
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help
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The EC firmware blob defaults to the 4MByte offset of the firmware
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image. If this offset needs to change, a new signature block must be
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generated with the updated offset.
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config VBOOT
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select VBOOT_NO_BOARD_SUPPORT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_STARTS_IN_BOOTBLOCK
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config VBOOT_VBNV_OFFSET
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hex
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default 0x2A
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config RO_REGION_ONLY
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string
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depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
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# Add the EFS and EC to the RO region only
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# This is a mayan-specific override of soc/amd/morgana/Kconfig
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default "apu/amdfw apu/ecfw"
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config CHROMEOS
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# Use default libpayload config
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select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
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# We don't have recovery buttons, so we can't manually enable devmode.
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
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config EFS_SPI_READ_MODE
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default 3 # Quad IO (1-1-4)
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config EFS_SPI_SPEED
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default 0 # 66MHz
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config EFS_SPI_MICRON_FLAG
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default 0
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config NORMAL_READ_SPI_SPEED
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default 1 # 33MHz
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config ALT_SPI_SPEED
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default 1 # 33MHz
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config TPM_SPI_SPEED
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default 1 # 33MHz
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endif # !EM100
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endif # BOARD_AMD_MAYAN_MORGANA
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@ -0,0 +1,5 @@
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comment "Mayan"
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config BOARD_AMD_MAYAN_MORGANA
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bool "-> Mayan for Morgana SoC"
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select SOC_AMD_MORGANA
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@ -0,0 +1,42 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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bootblock-y += early_gpio.c
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bootblock-y += ec.c
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romstage-y += port_descriptors.c
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ramstage-y += chromeos.c
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ramstage-y += gpio.c
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ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin),)
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin
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APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_DefaultRecovery.bin
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else
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$(info APCB sources not found. Skipping APCB. The resulting image won't boot.)
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endif
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ifeq ($(CONFIG_MAYAN_HAVE_MCHP_FW),y)
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$(call add_intermediate, add_mchp_fw)
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$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MAYAN_MCHP_SIG_FILE) --fill-upward
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# calculate the absolute position from the config offset
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MAYAN_EC_POSITION=$(call int-add, \
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$(call int-subtract, 0xffffffff \
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$(CONFIG_ROM_SIZE)) $(CONFIG_MAYAN_MCHP_FW_OFFSET) 1)
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cbfs-files-y += apu/ecfw
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apu/ecfw-file := $(CONFIG_MAYAN_MCHP_FW_FILE)
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apu/ecfw-position := $(MAYAN_EC_POSITION)
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apu/ecfw-type := raw
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else
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files_added:: warn_no_mchp
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endif # CONFIG_MAYAN_HAVE_MCHP_FW
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PHONY+=warn_no_mchp
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warn_no_mchp:
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printf "\n\t** WARNING **\n"
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printf "coreboot has been built without the EC FW.\n"
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printf "Do not flash this image. Your Mayan's power button\n"
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printf "will not respond when you press it.\n\n"
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@ -0,0 +1,8 @@
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FLASH@0xFF000000 16M {
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BIOS {
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EC 4K
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RW_MRC_CACHE 120K
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FMAP 4K
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COREBOOT(CBFS)
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}
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}
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@ -0,0 +1 @@
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Category: eval
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <soc/espi.h>
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#include "ec.h"
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#include "gpio.h"
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void bootblock_mainboard_early_init(void)
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{
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mainboard_program_early_gpios();
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espi_switch_to_spi1_pads();
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}
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void bootblock_mainboard_init(void)
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{
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mayan_ec_init();
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}
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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/* Mayan doesn't have a write protect pin */
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return 0;
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}
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DECLARE_NO_CROS_GPIOS();
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FLASH@0xFF000000 16M {
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SI_BIOS {
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EC 4K
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RW_MRC_CACHE(PRESERVE) 120K
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RW_SECTION_A 4M {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 256
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}
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RW_SECTION_B 4M {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 256
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}
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 20K
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SMMSTORE(PRESERVE) 64K
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RW_LEGACY(CBFS)
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WP_RO@10M 6M {
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RO_VPD(PRESERVE) 16K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 448K
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COREBOOT(CBFS)
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}
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}
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}
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}
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@ -0,0 +1,226 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# TODO: Update for mayan
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chip soc/amd/morgana
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register "common_config.espi_config" = "{
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.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
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.generic_io_range[0] = {
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.base = 0x3f8,
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.size = 8,
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},
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.generic_io_range[1] = {
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.base = 0x600,
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.size = 256,
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},
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.io_mode = ESPI_IO_MODE_QUAD,
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.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
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.crc_check_enable = 1,
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.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
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.periph_ch_en = 1,
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.vw_ch_en = 1,
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.oob_ch_en = 1,
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.flash_ch_en = 0,
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}"
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register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
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GPIO_I2C2_SCL | GPIO_I2C3_SCL"
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register "i2c[0].early_init" = "1"
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register "i2c[1].early_init" = "1"
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register "i2c[2].early_init" = "1"
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register "i2c[3].early_init" = "1"
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# I2C Pad Control RX Select Configuration
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register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
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register "s0ix_enable" = "true"
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register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
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register "usb_phy_custom" = "1"
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register "usb_phy" = "{
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.Usb2PhyPort[0] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[1] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[2] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[3] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[4] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[5] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb3PhyPort[0] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.Usb3PhyPort[1] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.Usb3PhyPort[2] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
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.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
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.BatteryChargerEnable = 0,
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.PhyP3CpmP4Support = 0,
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}"
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register "gpp_clk_config[0]" = "GPP_CLK_REQ"
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register "gpp_clk_config[1]" = "GPP_CLK_REQ"
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register "gpp_clk_config[2]" = "GPP_CLK_OFF"
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register "gpp_clk_config[3]" = "GPP_CLK_REQ"
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device domain 0 on
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device ref iommu on end
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device ref gpp_bridge_0 on end # GBE
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device ref gpp_bridge_1 on end # WIFI
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device ref gpp_bridge_2 on end # NVMe SSD
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref gfx on end # Internal GPU (GFX)
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device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
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device ref crypto on end # Crypto Coprocessor
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device ref xhci_0 on # USB 3.1 (USB0)
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chip drivers/usb/acpi
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device ref xhci_0_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port0 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port0 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port1 on end
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end
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end
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end
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end
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device ref xhci_1 on # USB 3.1 (USB1)
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chip drivers/usb/acpi
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device ref xhci_1_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port2 on end
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end
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chip drivers/usb/acpi
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device ref usb3_port3 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref acp on end # Audio Processor (ACP)
|
||||
end
|
||||
device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
|
||||
device ref xhci_2 on
|
||||
chip drivers/usb/acpi
|
||||
register "type" = "UPC_TYPE_HUB"
|
||||
device usb 0.0 alias xhci_2_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
device usb 2.0 alias usb2_port5 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
device ref i2c_0 on end
|
||||
device ref i2c_1 on end
|
||||
device ref i2c_2 on end
|
||||
device ref i2c_3 on end
|
||||
device ref uart_0 on end # UART0
|
||||
|
||||
end
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock (
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
|
||||
#include <soc.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include "gpio.h"
|
||||
|
||||
/* TODO: Update for mayan */
|
||||
|
||||
/* GPIO pins used by coreboot should be initialized in bootblock */
|
||||
|
||||
static const struct soc_amd_gpio gpio_set_stage_reset[] = {
|
||||
};
|
||||
|
||||
void mainboard_program_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
|
||||
}
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* TODO: Update for mayan */
|
||||
|
||||
#include <ec/acpi/ec.h>
|
||||
#include "ec.h"
|
||||
|
||||
#define MAYAN_EC_CMD 0x666
|
||||
#define MAYAN_EC_DATA 0x662
|
||||
|
||||
#define EC_GPIO_3_ADDR 0xA3
|
||||
#define EC_GPIO_LOM_RESET_AUX BIT(1)
|
||||
|
||||
#define EC_GPIO_7_ADDR 0xA7
|
||||
#define EC_GPIO_DT_PWREN BIT(2)
|
||||
#define EC_GPIO_WWAN_MODULE_RST BIT(5)
|
||||
|
||||
#define EC_GPIO_8_ADDR 0xA8
|
||||
#define EC_GPIO_SMBUS0_EN BIT(0)
|
||||
|
||||
#define EC_GPIO_A_ADDR 0xAA
|
||||
#define EC_GPIO_WWAN_PWREN BIT(3)
|
||||
#define EC_GPIO_M2_SSD0_PWREN BIT(6)
|
||||
#define EC_GPIO_LOM_PWREN BIT(7)
|
||||
|
||||
#define EC_GPIO_C_ADDR 0xAC
|
||||
#define EC_GPIO_DT_N_WLAN_SW BIT(1)
|
||||
#define EC_GPIO_MP2_SEL BIT(2)
|
||||
#define EC_GPIO_WWAN_N_LOM_SW BIT(3)
|
||||
|
||||
#define EC_SW02_ADDR 0xB7
|
||||
#define EC_SW02_MS BIT(7)
|
||||
|
||||
static void configure_ec_gpio(void)
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
tmp = ec_read(EC_GPIO_3_ADDR);
|
||||
tmp |= EC_GPIO_LOM_RESET_AUX;
|
||||
ec_write(EC_GPIO_3_ADDR, tmp);
|
||||
|
||||
tmp = ec_read(EC_GPIO_7_ADDR);
|
||||
tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN;
|
||||
ec_write(EC_GPIO_7_ADDR, tmp);
|
||||
|
||||
tmp = ec_read(EC_GPIO_8_ADDR);
|
||||
tmp |= EC_GPIO_SMBUS0_EN;
|
||||
ec_write(EC_GPIO_8_ADDR, tmp);
|
||||
|
||||
tmp = ec_read(EC_GPIO_A_ADDR);
|
||||
tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN;
|
||||
ec_write(EC_GPIO_A_ADDR, tmp);
|
||||
|
||||
tmp = ec_read(EC_GPIO_C_ADDR);
|
||||
tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW;
|
||||
ec_write(EC_GPIO_C_ADDR, tmp);
|
||||
|
||||
tmp = ec_read(EC_SW02_ADDR);
|
||||
tmp |= EC_SW02_MS;
|
||||
ec_write(EC_SW02_ADDR, tmp);
|
||||
}
|
||||
|
||||
void mayan_ec_init(void)
|
||||
{
|
||||
ec_set_ports(MAYAN_EC_CMD, MAYAN_EC_DATA);
|
||||
configure_ec_gpio();
|
||||
}
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAYAN_EC_H
|
||||
#define MAYAN_EC_H
|
||||
|
||||
void mayan_ec_init(void);
|
||||
|
||||
#endif /* MAYAN_EC_H */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include "gpio.h"
|
||||
|
||||
/* TODO: Update for mayan */
|
||||
|
||||
/*
|
||||
* As a rule of thumb, GPIO pins used by coreboot should be initialized at
|
||||
* bootblock while GPIO pins used only by the OS should be initialized at
|
||||
* ramstage.
|
||||
*/
|
||||
static const struct soc_amd_gpio gpio_set_stage_ram[] = {
|
||||
|
||||
};
|
||||
|
||||
void mainboard_program_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */
|
||||
void mainboard_program_gpios(void); /* ramstage GPIO configuration */
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/amd_pci_util.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <device/device.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <types.h>
|
||||
#include "gpio.h"
|
||||
|
||||
/* TODO: Update for mayan */
|
||||
|
||||
/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
|
||||
accessed via I/O ports 0xc00/0xc01. */
|
||||
|
||||
/*
|
||||
* This controls the device -> IRQ routing.
|
||||
*
|
||||
* Hardcoded IRQs:
|
||||
* 0: timer < soc/amd/common/acpi/lpc.asl
|
||||
* 1: i8042 - Keyboard
|
||||
* 2: cascade
|
||||
* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
|
||||
* 9: acpi <- soc/amd/common/acpi/lpc.asl
|
||||
*/
|
||||
static const struct fch_irq_routing fch_irq_map[] = {
|
||||
{ PIRQ_A, 12, PIRQ_NC },
|
||||
{ PIRQ_B, 14, PIRQ_NC },
|
||||
{ PIRQ_C, 15, PIRQ_NC },
|
||||
{ PIRQ_D, 12, PIRQ_NC },
|
||||
{ PIRQ_E, 14, PIRQ_NC },
|
||||
{ PIRQ_F, 15, PIRQ_NC },
|
||||
{ PIRQ_G, 12, PIRQ_NC },
|
||||
{ PIRQ_H, 14, PIRQ_NC },
|
||||
|
||||
{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
|
||||
{ PIRQ_SD, PIRQ_NC, PIRQ_NC },
|
||||
{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
|
||||
{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
|
||||
{ PIRQ_GPIO, 11, 11 },
|
||||
{ PIRQ_I2C0, 10, 10 },
|
||||
{ PIRQ_I2C1, 7, 7 },
|
||||
{ PIRQ_I2C2, 6, 6 },
|
||||
{ PIRQ_I2C3, 5, 5 },
|
||||
{ PIRQ_UART0, 4, 4 },
|
||||
{ PIRQ_UART1, 3, 3 },
|
||||
|
||||
/* The MISC registers are not interrupt numbers */
|
||||
{ PIRQ_MISC, 0xfa, 0x00 },
|
||||
{ PIRQ_MISC0, 0x91, 0x00 },
|
||||
{ PIRQ_HPET_L, 0x00, 0x00 },
|
||||
{ PIRQ_HPET_H, 0x00, 0x00 },
|
||||
};
|
||||
|
||||
const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
|
||||
{
|
||||
*length = ARRAY_SIZE(fch_irq_map);
|
||||
return fch_irq_map;
|
||||
}
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
mainboard_program_gpios();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/i2c_simple.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/platform_descriptors.h>
|
||||
#include <types.h>
|
||||
|
||||
/* TODO: Update for mayan */
|
||||
|
||||
static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
|
||||
{
|
||||
.engine_type = PCIE_ENGINE,
|
||||
.port_present = true,
|
||||
.start_logical_lane = 0,
|
||||
.end_logical_lane = 0,
|
||||
.device_number = 2,
|
||||
.function_number = 1,
|
||||
.link_speed_capability = GEN3,
|
||||
.turn_off_unused_lanes = true,
|
||||
.link_aspm = 2,
|
||||
.link_hotplug = 3,
|
||||
.clk_req = CLK_REQ3,
|
||||
},
|
||||
{
|
||||
.engine_type = PCIE_ENGINE,
|
||||
.port_present = true,
|
||||
.start_logical_lane = 1,
|
||||
.end_logical_lane = 1,
|
||||
.device_number = 2,
|
||||
.function_number = 2,
|
||||
.link_speed_capability = GEN3,
|
||||
.turn_off_unused_lanes = true,
|
||||
.link_aspm = 2,
|
||||
.link_hotplug = 3,
|
||||
.clk_req = CLK_REQ1,
|
||||
},
|
||||
{
|
||||
.engine_type = PCIE_ENGINE,
|
||||
.port_present = true,
|
||||
.start_logical_lane = 2,
|
||||
.end_logical_lane = 3,
|
||||
.device_number = 2,
|
||||
.function_number = 3,
|
||||
.link_speed_capability = GEN3,
|
||||
.turn_off_unused_lanes = true,
|
||||
.link_aspm = 2,
|
||||
.link_hotplug = 3,
|
||||
.gpio_group_id = GPIO_27,
|
||||
.clk_req = CLK_REQ0,
|
||||
},
|
||||
};
|
||||
|
||||
static fsp_ddi_descriptor mayan_ddi_descriptors[] = {
|
||||
{ /* DDI0 - eDP */
|
||||
.connector_type = DDI_EDP,
|
||||
.aux_index = DDI_AUX1,
|
||||
.hdp_index = DDI_HDP1
|
||||
},
|
||||
{ /* DDI1 - HDMI/DP */
|
||||
.connector_type = DDI_HDMI,
|
||||
.aux_index = DDI_AUX2,
|
||||
.hdp_index = DDI_HDP2
|
||||
},
|
||||
{ /* DDI2 - DP (type C) */
|
||||
.connector_type = DDI_DP,
|
||||
.aux_index = DDI_AUX3,
|
||||
.hdp_index = DDI_HDP3,
|
||||
},
|
||||
{ /* DDI3 - DP (type C) */
|
||||
.connector_type = DDI_DP,
|
||||
.aux_index = DDI_AUX4,
|
||||
.hdp_index = DDI_HDP4,
|
||||
},
|
||||
{ /* DDI4 - unused */
|
||||
.connector_type = DDI_UNUSED_TYPE,
|
||||
.aux_index = DDI_AUX5,
|
||||
.hdp_index = DDI_HDP5,
|
||||
}
|
||||
};
|
||||
|
||||
static uint8_t get_ddi1_type(void)
|
||||
{
|
||||
const uint8_t eeprom_i2c_bus = 2;
|
||||
const uint8_t eeprom_i2c_address = 0x55;
|
||||
const uint16_t eeprom_connector_type_offset = 2;
|
||||
uint8_t eeprom_connector_type_data[2];
|
||||
uint16_t connector_type;
|
||||
|
||||
if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address,
|
||||
eeprom_connector_type_offset, eeprom_connector_type_data,
|
||||
sizeof(eeprom_connector_type_data))) {
|
||||
printk(BIOS_NOTICE,
|
||||
"Display connector type couldn't be determined. Disabling DDI1.\n");
|
||||
return DDI_UNUSED_TYPE;
|
||||
}
|
||||
|
||||
connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8;
|
||||
|
||||
switch (connector_type) {
|
||||
case 0xc:
|
||||
printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n");
|
||||
return DDI_HDMI;
|
||||
break;
|
||||
case 0x13:
|
||||
printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n");
|
||||
return DDI_DP;
|
||||
break;
|
||||
case 0x14:
|
||||
printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n");
|
||||
return DDI_EDP;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n",
|
||||
connector_type);
|
||||
return DDI_UNUSED_TYPE;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_get_dxio_ddi_descriptors(
|
||||
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
|
||||
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
|
||||
{
|
||||
mayan_ddi_descriptors[1].connector_type = get_ddi1_type();
|
||||
|
||||
*dxio_descs = mayan_dxio_descriptors;
|
||||
*dxio_num = ARRAY_SIZE(mayan_dxio_descriptors);
|
||||
*ddi_descs = mayan_ddi_descriptors;
|
||||
*ddi_num = ARRAY_SIZE(mayan_ddi_descriptors);
|
||||
}
|
||||
Loading…
Reference in New Issue