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soc/intel/apollolake/pmutil.c: Use {read,wrire}32p() 

Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Elyes Haouas 2022-12-11 10:28:59 +01:00 committed by Felix Held
parent b988f8aac5
commit f12c2b0837
1 changed files with 8 additions and 8 deletions
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16
src/soc/intel/apollolake/pmutil.c
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@ -133,9 +133,9 @@ void soc_clear_pm_registers(uintptr_t pmc_bar)
{ {
uint32_t gen_pmcon1; uint32_t gen_pmcon1;
gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1);
/* Clear the status bits. The RPS field is cleared on a 0 write. */ /* Clear the status bits. The RPS field is cleared on a 0 write. */
write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1 & ~RPS); write32p(pmc_bar + GEN_PMCON1, gen_pmcon1 & ~RPS);
} }
void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
@ -157,10 +157,10 @@ void soc_fill_power_state(struct chipset_power_state *ps)
ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco1_sts = tco_read_reg(TCO1_STS);
ps->tco2_sts = tco_read_reg(TCO2_STS); ps->tco2_sts = tco_read_reg(TCO2_STS);
ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->prsts = read32p(pmc_bar0 + PRSTS);
ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); ps->gen_pmcon1 = read32p(pmc_bar0 + GEN_PMCON1);
ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); ps->gen_pmcon2 = read32p(pmc_bar0 + GEN_PMCON2);
ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); ps->gen_pmcon3 = read32p(pmc_bar0 + GEN_PMCON3);
printk(BIOS_DEBUG, "prsts: %08x\n", printk(BIOS_DEBUG, "prsts: %08x\n",
ps->prsts); ps->prsts);
@ -200,7 +200,7 @@ int soc_get_rtc_failed(void)
int vbnv_cmos_failed(void) int vbnv_cmos_failed(void)
{ {
uintptr_t pmc_bar = soc_read_pmc_base(); uintptr_t pmc_bar = soc_read_pmc_base();
uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); uint32_t gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1);
int rtc_failure = rtc_failed(gen_pmcon1); int rtc_failure = rtc_failed(gen_pmcon1);
if (rtc_failure) { if (rtc_failure) {
@ -212,7 +212,7 @@ int vbnv_cmos_failed(void)
/* RPS is write 0 to clear. */ /* RPS is write 0 to clear. */
gen_pmcon1 &= ~RPS; gen_pmcon1 &= ~RPS;
write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1); write32p(pmc_bar + GEN_PMCON1, gen_pmcon1);
} }
return rtc_failure; return rtc_failure;