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mb/lenovo/t420/devicetree: Use subsystemid inheritance 

Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Peter Lemenkov 2019-11-27 12:04:42 +01:00 committed by Patrick Georgi
parent 322635a955
commit f15f310ea4
1 changed files with 14 additions and 36 deletions
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50
src/mainboard/lenovo/t420/devicetree.cb
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@ -37,13 +37,11 @@ chip northbridge/intel/sandybridge
register "pci_mmio_size" = "2048" register "pci_mmio_size" = "2048"
device domain 0 on device domain 0 on
device pci 00.0 on subsystemid 0x17aa 0x21ce inherit
subsystemid 0x17aa 0x21ce
end # host bridge device pci 00.0 on end # host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on device pci 02.0 on end # Integrated Graphics Controller
subsystemid 0x17aa 0x21ce
end # Integrated Graphics Controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing # GPI routing
@ -67,6 +65,7 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported register "c2_latency" = "101" # c2 not supported
# device specific SPI configuration # device specific SPI configuration
@ -77,46 +76,30 @@ chip northbridge/intel/sandybridge
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT device pci 16.3 off end # Management Engine KT
device pci 19.0 on device pci 19.0 on end # Intel Gigabit Ethernet
subsystemid 0x17aa 0x21ce device pci 1a.0 on end # USB Enhanced Host Controller #2
end # Intel Gigabit Ethernet device pci 1b.0 on end # High Definition Audio Controller
device pci 1a.0 on
subsystemid 0x17aa 0x21ce
end # USB Enhanced Host Controller #2
device pci 1b.0 on
subsystemid 0x17aa 0x21ce
end # High Definition Audio Controller
device pci 1c.0 off end # PCIe Port #1 device pci 1c.0 off end # PCIe Port #1
device pci 1c.1 on device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN
subsystemid 0x17aa 0x21ce
end # PCIe Port #2 Integrated Wireless LAN
device pci 1c.2 off end # PCIe Port #3 device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 on device pci 1c.3 on
subsystemid 0x17aa 0x21ce
smbios_slot_desc "7" "3" "ExpressCard Slot" "8" smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end # PCIe Port #4 ExpressCard end # PCIe Port #4 ExpressCard
device pci 1c.4 on device pci 1c.4 on
subsystemid 0x17aa 0x21ce
chip drivers/ricoh/rce822 chip drivers/ricoh/rce822
register "sdwppol" = "1" register "sdwppol" = "1"
register "disable_mask" = "0x87" register "disable_mask" = "0x87"
device pci 00.0 on device pci 00.0 on end
subsystemid 0x17aa 0x21ce
end
end end
end # PCIe Port #5 (Ricoh SD & FW) end # PCIe Port #5 (Ricoh SD & FW)
device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
device pci 1c.6 off end # PCIe Port #7 device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8 device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on device pci 1d.0 on end # USB Enhanced Host Controller #1
subsystemid 0x17aa 0x21ce
end # USB Enhanced Host Controller #1
device pci 1e.0 off end # PCI bridge device pci 1e.0 off end # PCI bridge
device pci 1f.0 on device pci 1f.0 on
subsystemid 0x17aa 0x21ce
chip ec/lenovo/pmh7 chip ec/lenovo/pmh7
device pnp ff.1 on # dummy device pnp ff.1 on end # dummy
end
register "backlight_enable" = "0x01" register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01" register "dock_event_enable" = "0x01"
end end
@ -176,11 +159,8 @@ chip northbridge/intel/sandybridge
register "has_thinker1" = "1" register "has_thinker1" = "1"
end end
end # LPC Controller end # LPC Controller
device pci 1f.2 on device pci 1f.2 on end # 6 port SATA AHCI Controller
subsystemid 0x17aa 0x21ce
end # 6 port SATA AHCI Controller
device pci 1f.3 on device pci 1f.3 on
subsystemid 0x17aa 0x21ce
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
@ -194,9 +174,7 @@ chip northbridge/intel/sandybridge
end end
end # SMBus Controller end # SMBus Controller
device pci 1f.5 off end # SATA Controller 2 device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on device pci 1f.6 on end # Thermal
subsystemid 0x17aa 0x21ce
end # Thermal
end end
end end
end end