google/chell: Add new mainboard for chell

This is based on glados with minor changes: - updated GPIOs based on schematic - add _PRW for trackpad wake now that it is on a new GPIO - add SPD for new memory config - disable ALS BUG=chrome-os-partner:46289 BRANCH=none TEST=emerge-chell coreboot Change-Id: Id5746bf2b5b26000fcc3f029b901bfe29b788dac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c5ebe98cf599ba80aac5e9ef238b7996789a819 Original-Change-Id: I75efda64a50b0e6e4a5c9008ce05d76c1e605b0c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304927 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12151 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-09 09:25:32 -07:00 · 2015-10-09 09:25:32 -07:00 · f16bb7cce3
parent 09170f16a4
commit f16bb7cce3
7 changed files with 78 additions and 61 deletions
--- a/src/mainboard/google/chell/Makefile.inc
+++ b/src/mainboard/google/chell/Makefile.inc
@ -22,7 +22,6 @@ subdirs-y += spd
 romstage-y += boardid.c
 romstage-y += pei_data.c

-verstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c

--- a/src/mainboard/google/chell/acpi/ec.asl
+++ b/src/mainboard/google/chell/acpi/ec.asl
@ -21,9 +21,6 @@
 #include "../ec.h"
 #include "../gpio.h"

-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT

--- a/src/mainboard/google/chell/acpi/mainboard.asl
+++ b/src/mainboard/google/chell/acpi/mainboard.asl
@ -21,6 +21,7 @@

 #define BOARD_TOUCHPAD_I2C_ADDR			0x15
 #define BOARD_TOUCHPAD_IRQ			TOUCHPAD_INT_L
+#define BOARD_TOUCHPAD_WAKE			GPE_TOUCHPAD_WAKE

 #define BOARD_TOUCHSCREEN_I2C_ADDR		0x10
 #define BOARD_TOUCHSCREEN_IRQ			TOUCHSCREEN_INT_L
@ -111,6 +112,7 @@ Scope (\_SB.PCI0.I2C1)
 		Name (_DDN, "Elan Touchpad")
 		Name (_UID, 1)
 		Name (_S0W, 4)
+		Name (_PRW, Package () { BOARD_TOUCHPAD_WAKE, 3 })

 		Name (_CRS, ResourceTemplate ()
 		{
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@ -54,16 +54,16 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[4]" = "2"

 	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
-	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
-	register "PortUsb20Enable[2]" = "1"	# Bluetooth
-	register "PortUsb20Enable[4]" = "1"	# Type-A Port 1
-	register "PortUsb20Enable[6]" = "1"	# Camera
-	register "PortUsb20Enable[8]" = "1"	# Type-A Port 2
+	register "PortUsb20Enable[1]" = "1"	# Type-A Port
+	register "PortUsb20Enable[2]" = "1"	# Camera
+	register "PortUsb20Enable[3]" = "1"	# Bluetooth
+	register "PortUsb20Enable[4]" = "1"	# SD
+	register "PortUsb20Enable[5]" = "1"	# Type-C Port 2

 	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
 	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
-	register "PortUsb30Enable[2]" = "1"	# Type-A Port 1
-	register "PortUsb30Enable[3]" = "1"	# Type-A Port 2
+	register "PortUsb30Enable[2]" = "1"	# Type-A Port
+	register "PortUsb30Enable[3]" = "1"	# SD

 	# USB Per Port HS Preemphasis Bias
 	register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
--- a/src/mainboard/google/chell/gpio.h
+++ b/src/mainboard/google/chell/gpio.h
@ -41,6 +41,9 @@
 /* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
 #define GPE_WLAN_WAKE		GPE0_DW0_16

+/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_TOUCHPAD_WAKE	GPE0_DW0_05
+
 /* Input device interrupt configuration */
 #define TOUCHPAD_INT_L		GPP_B3_IRQ
 #define TOUCHSCREEN_INT_L	GPP_E7_IRQ
@ -67,10 +70,10 @@ static const struct pad_config gpio_table[] = {
 /* PME# */		/* GPP_A11 */
 /* BM_BUSY# */		/* GPP_A12 */
 /* SUSWARN# */		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* SUS_STAT# */		PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* SUS_STAT# */		/* GPP_A14 */
 /* SUSACK# */		PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
-/* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
-/* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+/* SD_1P8_SEL */	/* GPP_A16 */
+/* SD_PWR_EN# */	/* GPP_A17 */
 /* ISH_GP0 */		/* GPP_A18 */
 /* ISH_GP1 */		/* GPP_A19 */
 /* ISH_GP2 */		/* GPP_A20 */
@ -80,15 +83,15 @@ static const struct pad_config gpio_table[] = {
 /* CORE_VID0 */		/* GPP_B0 */
 /* CORE_VID1 */		/* GPP_B1 */
 /* VRALERT# */		/* GPP_B2 */
-/* CPU_GP2 */		PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */
+/* CPU_GP2 */		PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */
 /* CPU_GP3 */		/* GPP_B4 */
-/* SRCCLKREQ0# */	/* GPP_B5 */
-/* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */
-/* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
+/* SRCCLKREQ0# */	PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */
+/* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */
+/* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */
 /* SRCCLKREQ3# */	/* GPP_B8 */
 /* SRCCLKREQ4# */	/* GPP_B9 */
 /* SRCCLKREQ5# */	/* GPP_B10 */
-/* EXT_PWR_GATE# */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* EXT_PWR_GATE# */	/* GPP_B11 */
 /* SLP_S0# */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PLTRST# */		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 /* SPKR */		/* GPP_B14 */
@ -100,15 +103,15 @@ static const struct pad_config gpio_table[] = {
 /* GSPI1_CLK */		/* GPP_B20 */
 /* GSPI1_MISO */	/* GPP_B21 */
 /* GSPI1_MOSI */	/* GPP_B22 */
-/* SM1ALERT# */		/* GPP_B23 */
+/* SM1ALERT# */		PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */
 /* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
 /* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
 /* SMBALERT# */		/* GPP_C2 */
-/* SML0CLK */		/* GPP_C3 */
-/* SML0DATA */		/* GPP_C4 */
-/* SML0ALERT# */	/* GPP_C5 */
+/* SML0CLK */		PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */
+/* SML0DATA */		PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */
+/* SML0ALERT# */	PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */
 /* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */		/* GPP_C7 */
+/* SM1DATA */		PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */
 /* UART0_RXD */		/* GPP_C8 */
 /* UART0_TXD */		/* GPP_C9 */
 /* UART0_RTS# */	/* GPP_C10 */
@ -125,29 +128,29 @@ static const struct pad_config gpio_table[] = {
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
 /* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
-			/* GPP_D0 */
-			/* GPP_D1 */
-			/* GPP_D2 */
-			/* GPP_D3 */
+/* SPI1_CS# */		/* GPP_D0 */
+/* SPI1_CLK */		/* GPP_D1 */
+/* SPI1_MISO */		/* GPP_D2 */
+/* SPI1_MOSI */		/* GPP_D3 */
 /* FASHTRIG */		/* GPP_D4 */
 /* ISH_I2C0_SDA */	PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
 /* ISH_I2C0_SCL */	PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
 /* ISH_I2C1_SDA */	/* GPP_D7 */
 /* ISH_I2C1_SCL */	/* GPP_D8 */
-			/* GPP_D9 */
-			PAD_CFG_GPO(GPP_D10, 1, DEEP), /* USBA_1_ILIM_SEL_L */
-			PAD_CFG_GPO(GPP_D11, 1, DEEP), /* USBA_2_ILIM_SEL_L */
-			PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
+/* ISH_SPI_CS# */	/* GPP_D9 */
+/* ISH_SPI_CLK */	PAD_CFG_GPO(GPP_D10, 1, DEEP), /* USBA_1_ILIM_SEL_L */
+/* ISH_SPI_MISO */	/* GPP_D11 */
+/* ISH_SPI_MOSI */	PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
 /* ISH_UART0_RXD */	/* GPP_D13 */
 /* ISH_UART0_TXD */	/* GPP_D14 */
 /* ISH_UART0_RTS# */	/* GPP_D15 */
 /* ISH_UART0_CTS# */	/* GPP_D16 */
-/* DMIC_CLK1 */		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-/* DMIC_DATA1 */	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* DMIC_CLK1 */		/* GPP_D17 */
+/* DMIC_DATA1 */	/* GPP_D18 */
 /* DMIC_CLK0 */		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 /* DMIC_DATA0 */	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-			/* GPP_D21 */
-			/* GPP_D22 */
+/* SPI1_IO2 */		/* GPP_D21 */
+/* SPI1_IO3 */		/* GPP_D22 */
 /* I2S_MCLK */		PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 /* SATAXPCI0 */		PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */
 /* SATAXPCIE1 */	/* GPP_E1 */
@ -156,14 +159,14 @@ static const struct pad_config gpio_table[] = {
 /* SATA_DEVSLP0 */	/* GPP_E4 */
 /* SATA_DEVSLP1 */	/* GPP_E5 */
 /* SATA_DEVSLP2 */	/* GPP_E6 */
-/* CPU_GP1 */		PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */
+/* CPU_GP1 */		PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */
 /* SATALED# */		/* GPP_E8 */
-/* USB2_OCO# */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
-/* USB2_OC1# */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
-/* USB2_OC2# */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
-/* USB2_OC3# */		PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
-/* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
-/* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+/* USB2_OCO# */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */
+/* USB2_OC1# */		/* GPP_E10 */
+/* USB2_OC2# */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */
+/* USB2_OC3# */		PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */
+/* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */
+/* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */
 /* DDPD_HPD2 */		PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */
 /* DDPE_HPD3 */		PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
@ -171,8 +174,8 @@ static const struct pad_config gpio_table[] = {
 /* DDPB_CTRLDATA */	/* GPP_E19 */
 /* DDPC_CTRLCLK */	/* GPP_E20 */
 /* DDPC_CTRLDATA */	/* GPP_E21 */
-			/* GPP_E22 */
-			/* GPP_E23 */
+/* DDPD_CTRLCLK */	/* GPP_E22 */
+/* DDPD_CTRLDATA */	/* GPP_E23 */
 /*
 * The next 4 pads are for bit banging the amplifiers. They are connected
 * together with i2s0 signals. For default behavior of i2s make these
@ -186,8 +189,8 @@ static const struct pad_config gpio_table[] = {
 /* I2C2_SCL */		/* GPP_F5 */
 /* I2C3_SDA */		/* GPP_F6 */
 /* I2C3_SCL */		/* GPP_F7 */
-/* I2C4_SDA */		PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */
-/* I2C4_SCL */		PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */
+/* I2C4_SDA */		PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
+/* I2C4_SCL */		PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
 /* I2C5_SDA */		PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */
 /* I2C5_SCL */		/* GPP_F11 */
 /* EMMC_CMD */		PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
@ -201,26 +204,26 @@ static const struct pad_config gpio_table[] = {
 /* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 /* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 /* EMMC_CLK */		PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-			/* GPP_F23 */
-/* SD_CMD */		PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
-/* SD_DATA0 */		PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
-/* SD_DATA1 */		PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
-/* SD_DATA2 */		PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
-/* SD_DATA3 */		PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
-/* SD_CD# */		PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
-/* SD_CLK */		PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
-/* SD_WP */		PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
-/* BATLOW# */		/* GPD0 */
+/* RSVD */		/* GPP_F23 */
+/* SD_CMD */		/* GPP_G0 */
+/* SD_DATA0 */		/* GPP_G1 */
+/* SD_DATA1 */		/* GPP_G2 */
+/* SD_DATA2 */		/* GPP_G3 */
+/* SD_DATA3 */		/* GPP_G4 */
+/* SD_CD# */		/* GPP_G5 */
+/* SD_CLK */		/* GPP_G6 */
+/* SD_WP */		/* GPP_G7 */
+/* BATLOW# */		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 /* ACPRESENT */		PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 /* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
 /* PWRBTN# */		PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 /* SLP_S3# */		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 /* SLP_S4# */		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-/* SLP_A# */		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
-			/* GPD7 */
+/* SLP_A# */		/* GPD6 */
+/* RSVD */		/* GPD7 */
 /* SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 /* SLP_WLAN# */		/* GPD9 */
-/* SLP_S5# */		PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+/* SLP_S5# */		/* GPD10 */
 /* LANPHYC */		/* GPD11 */
 };

--- a/src/mainboard/google/chell/spd/Makefile.inc
+++ b/src/mainboard/google/chell/spd/Makefile.inc
@ -23,7 +23,7 @@ romstage-y += spd.c
 SPD_BIN = $(obj)/spd.bin

 # SPD data by index.  No method for board identification yet
-SPD_SOURCES = empty                             # 0b0000
+SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCF      # 0b0000
 SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF     # 0b0001
 SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR        # 0b0010
 SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR        # 0b0011
--- a/src/mainboard/google/chell/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
+++ b/src/mainboard/google/chell/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
@ -0,0 +1,16 @@
+91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
+4B 34 45 38 45 33 30 34 45 45 2D 45 47 43 46 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00