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RISC-V: Make inline asm usage safer 

Change-Id: Id547c98e876e9fd64fa4d12239a2608bfd2495d2
Signed-off-by: Andrew Waterman <aswaterman@gmail.com>
Reviewed-on: https://review.coreboot.org/13735
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Andrew Waterman 2016-02-18 16:06:21 -08:00 committed by Ronald G. Minnich
parent deba4e8560
commit f16d904192
1 changed files with 5 additions and 7 deletions
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12
src/arch/riscv/trap_handler.c
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@ -84,20 +84,18 @@ void handle_supervisor_call(trapframe *tf) {
void trap_handler(trapframe *tf) {
write_csr(mscratch, tf);
int cause = 0;
void* epc = 0;
void* badAddr = 0;
uintptr_t cause;
void *epc;
void *badAddr;
// extract cause
asm("csrr t0, mcause");
asm("move %0, t0" : "=r"(cause));
asm("csrr %0, mcause" : "=r"(cause));
// extract faulting Instruction pc
epc = (void*) tf->epc;
// extract bad address
asm("csrr t0, mbadaddr");
asm("move %0, t0" : "=r"(badAddr));
asm("csrr %0, mbadaddr" : "=r"(badAddr));
switch(cause) {
case 0: