mb/google/kblrvp: Add camera devices power sequencing through ACPI power resources
This patch controls the camera devices power through ACPI power resource. * Add Opregions for PMIC1 and PMIC2, * TI_PMIC_POWER_OPREGION * TI_PMIC_VR_VAL_OPREGION * TI_PMIC_CLK_OPREGION * TI_PMIC_CLK_FREQ_OPREGION * Add power resources for sensors and VCM, * OVTH for CAM0 * OVFI for CAM1 * VCMP for VCM * Implement _ON and _OFF methods for sensor and VCM module's power on and power off sequences. BUG=none BRANCH=none TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
V Sowmya
Martin Roth
parent
34e92a9be5
commit
f19ee0d737
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@ -27,13 +27,358 @@ Scope (\_SB.PCI0.I2C2)
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Return (0x0F)
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}
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/* Marks the availability of all the operation regions */
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Name (AVP1, Zero)
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Name (AVGP, Zero)
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Name (AVB0, Zero)
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Name (AVB1, Zero)
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Name (AVB2, Zero)
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Name (AVB3, Zero)
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Method (_REG, 2, NotSerialized)
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{
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If (LEqual (Arg0, 0x08))
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{
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/* Marks the availability of GeneralPurposeIO
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* 0x08: opregion space for GeneralPurposeIO
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*/
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Store (Arg1, AVGP)
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}
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If (LEqual (Arg0, 0xB0))
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{
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/* Marks the availability of
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* TI_PMIC_POWER_OPREGION_ID */
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Store (Arg1, AVB0)
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}
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If (LEqual (Arg0, 0xB1))
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{
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/* Marks the availability of
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* TI_PMIC_VR_VAL_OPREGION_ID */
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Store (Arg1, AVB1)
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}
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If (LEqual (Arg0, 0xB2))
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{
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/* Marks the availability of
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* TI_PMIC_CLK_OPREGION_ID */
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Store (Arg1, AVB2)
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}
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If (LEqual (Arg0, 0xB3))
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{
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/* Marks the availability of
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* TI_PMIC_CLK_FREQ_OPREGION_ID */
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Store (Arg1, AVB3)
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}
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If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1),
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LAnd(AVB2, AVB3))))
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{
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/* Marks the availability of all opregions */
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Store (1, AVP1)
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}
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Else
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{
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Store (0, AVP1)
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}
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}
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OperationRegion (GPOP, GeneralPurposeIo, 0, 0x2)
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Name (_CRS, ResourceTemplate ()
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{
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I2cSerialBus (0x004D, ControllerInitiated, 0x00061A80,
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AddressingMode7Bit, "\\_SB.PCI0.I2C2",
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0x00, ResourceConsumer, ,
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)
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/* GPIO.9 is XSHUTDOWN pin for world facing camera */
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GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
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IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC",
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0x00, ResourceConsumer,,)
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{
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9
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}
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})
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/* PMIC operation regions */
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/* 0xB0: TI_PMIC_POWER_OPREGION_ID
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* VSIO: Sensor IO LDO output
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* VCMC: VCM LDO output
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* VAX1: Auxiliary LDO1 output
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* VAX2: Auxiliary LDO2 output
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* VACT: Analog LDO output
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* VDCT: Core buck output
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*/
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OperationRegion (PWR1, 0xB0, Zero, 0x0100)
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Field (PWR1, DWordAcc, NoLock, Preserve)
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{
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VSIO, 32,
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VCMC, 32,
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VAX1, 32,
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VAX2, 32,
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VACT, 32,
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VDCT, 32,
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}
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/* 0xB1: TI_PMIC_VR_VAL_OPREGION_ID
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* SIOV: VSIO VR voltage value
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* IOVA: VIO VR voltage value
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* VCMV: VCM VR voltage value
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* AX1V: Auxiliary LDO1 VR voltage value
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* AX2V: Auxiliary LDO2 VR voltage value
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* ACVA: Analog LDO VR voltage
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* DCVA: Core buck VR volatage
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*/
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OperationRegion (PWR2, 0xB1, Zero, 0x0100)
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Field (PWR2, DWordAcc, NoLock, Preserve)
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{
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SIOV, 32,
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IOVA, 32,
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VCMV, 32,
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AX1V, 32,
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AX2V, 32,
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ACVA, 32,
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DCVA, 32,
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}
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/* 0xB2: TI_PMIC_CLK_OPREGION_ID
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* PCTL: PLL control register
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* PCT2: PLL control 2 register
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* CFG1: Clock configuration 1 register
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* CFG2: Clock configuration 2 register
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*/
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OperationRegion (CLKC, 0xB2, Zero, 0x0100)
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Field (CLKC, DWordAcc, NoLock, Preserve)
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{
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PCTL, 32,
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PCT2, 32,
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CFG1, 32,
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CFG2, 32,
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}
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/* 0xB3: TI_PMIC_CLK_FREQ_OPREGION_ID
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* PDV2: PLL output divider for HCLK_B
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* BODI: PLL output divider for boost clock
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* BUDI: PLL output divider for buck clock
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* PSWR: PLL reference clock setting
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* XTDV: Reference crystal divider
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* PLDV: PLL feedback divider
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* PODV: PLL output divider for HCLK_A
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*/
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OperationRegion (CLKF, 0xB3, Zero, 0x0100)
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Field (CLKF, DWordAcc, NoLock, Preserve)
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{
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PDV2, 32,
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BODI, 32,
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BUDI, 32,
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PSWR, 32,
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XTDV, 32,
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PLDV, 32,
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PODV, 32,
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}
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Mutex (MUTC, 0)
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Method (CLKE, 0, Serialized) {
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/* save Acquire result so we can check for
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Mutex acquired */
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Store (Acquire (MUTC, 1000), Local0)
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/* check for Mutex acquired */
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If (LEqual (Local0, Zero)) {
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/* Set boost clock divider */
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BODI = 3
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/* Set buck clock divider */
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BUDI = 2
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/* Set the PLL_REF_CLK cyles */
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PSWR = 19
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/* Set the reference crystal divider */
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XTDV = 170
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/* Set PLL feedback divider */
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PLDV = 32
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/* Set PLL output divider for HCLK_A */
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PODV = 1
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/* Enable HCLK_A clock.
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* CFG1: output selection for HCLK_A.
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* CFG2: set drive strength for HCLK_A.
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*/
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CFG2 = 1
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CFG1 = 2
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/* Enable PLL output, crystal oscillator
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* input capacitance control and set
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* Xtal oscillator as clock source.
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*/
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PCTL = 209
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Sleep(1)
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Release (MUTC)
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}
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}
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Method (CLKD, 0, Serialized) {
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/* save Acquire result so we can check for
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Mutex acquired */
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Store (Acquire (MUTC, 1000), Local0)
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/* check for Mutex acquired */
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If (LEqual (Local0, Zero)) {
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BODI = 0
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BUDI = 0
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PSWR = 0
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XTDV = 0
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PLDV = 0
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PODV = 0
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/* Disable HCLK_A clock */
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CFG2 = 0
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CFG1 = 0
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PCTL = 0
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Release (MUTC)
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}
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}
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/* Reference count for VSIO */
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Mutex (MUTV, 0)
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Name (VSIC, 0)
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Method (DOVD, 1, Serialized) {
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/* Save Acquire result so we can check for
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Mutex acquired */
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Store (Acquire (MUTV, 1000), Local0)
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/* Check for Mutex acquired */
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If (LEqual (Local0, Zero)) {
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/* Turn off VSIO */
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If (LEqual (Arg0, Zero)) {
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/* Decrement only if VSIC > 0 */
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if (LGreater (VSIC, 0)) {
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Decrement (VSIC)
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If (LEqual (VSIC, Zero)) {
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VSIO = 0
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}
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}
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} ElseIf (LEqual (Arg0, 1)) {
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/* Increment only if VSIC < 2 */
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If (LLess (VSIC, 2)) {
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/* Turn on VSIO */
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If (LEqual (VSIC, Zero)) {
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VSIO = 3
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}
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Increment (VSIC)
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}
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}
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Release (MUTV)
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}
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}
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/* Power resource methods for CAM0 */
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PowerResource (OVTH, 0, 0) {
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Name (STA, 0)
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Method (_ON, 0, Serialized) {
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If (LEqual (AVP1, 1)) {
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If (LEqual (STA, 0)) {
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/* Enable VSIO regulator +
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daisy chain */
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DOVD(1)
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if (LNotEqual (IOVA, 52)) {
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/* Set VSIO value as
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1.8006 V */
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IOVA = 52
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}
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if (LNotEqual (SIOV, 52)) {
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/* Set VSIO value as
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1.8006 V */
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SIOV = 52
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}
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Sleep(3)
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VACT = 1
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if (LNotEqual (ACVA, 109)) {
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/* Set ANA at 2.8152V */
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ACVA = 109
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}
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Sleep(3)
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\_SB.PCI0.I2C2.PMIC.CLKE()
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VDCT = 1
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if (LNotEqual (DCVA, 12)) {
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/* Set CORE at 1.2V */
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DCVA = 12
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}
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Sleep(3)
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\_SB.PCI0.I2C2.CAM0.CRST(1)
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Sleep(5)
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STA = 1
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}
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}
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}
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Method (_OFF, 0, Serialized) {
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If (LEqual (AVP1, 1)) {
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If (LEqual (STA, 1)) {
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Sleep(2)
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\_SB.PCI0.I2C2.PMIC.CLKD()
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Sleep(2)
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\_SB.PCI0.I2C2.CAM0.CRST(0)
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Sleep(3)
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VDCT = 0
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Sleep(3)
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VACT = 0
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Sleep(1)
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DOVD(0)
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Sleep(1)
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}
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}
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STA = 0
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}
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Method (_STA, 0, NotSerialized) {
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Return (STA)
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}
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}
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/* Power resource methods for VCM */
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PowerResource (VCMP, 0, 0) {
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Name (STA, 0)
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Method (_ON, 0, Serialized) {
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If (LEqual (AVP1, 1)) {
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If (LEqual (STA, 0)) {
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/* Enable VSIO regulator +
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daisy chain */
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DOVD(1)
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if (LNotEqual (IOVA, 52)) {
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/* Set VSIO value as
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1.8006 V */
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IOVA = 52
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}
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if (LNotEqual (SIOV, 52)) {
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/* Set VSIO value as
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1.8006 V */
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SIOV = 52
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}
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Sleep(3)
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/* Enable VCM regulator */
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VCMC = 1
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if (LNotEqual (VCMV, 109)) {
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/* Set VCM value at
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2.8152 V */
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VCMV = 109
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}
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Sleep(3)
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STA = 1
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}
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}
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}
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Method (_OFF, 0, Serialized) {
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If (LEqual (AVP1, 1)) {
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If (LEqual (STA, 1)) {
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VCMC = 0 /* Disable regulator */
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Sleep(1)
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DOVD(0) /* Disable regulator */
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Sleep(1)
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STA = 0
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}
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}
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}
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Method (_STA, 0, NotSerialized) {
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Return (STA)
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}
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}
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}
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Device (CAM0)
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@ -57,6 +402,30 @@ Scope (\_SB.PCI0.I2C2)
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)
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})
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Field (\_SB.PCI0.I2C2.PMIC.GPOP, ByteAcc, NoLock, Preserve)
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{
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Connection
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(
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GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
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IoRestrictionOutputOnly,
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"\\_SB.PCI0.I2C2.PMIC", 0x00,
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ResourceConsumer,,)
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{
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9
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}
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),
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GRST, 1,
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}
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/* Set or clear GRST GPIO */
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Method (CRST, 1, Serialized)
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{
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GRST = Arg0
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}
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Name (_PR0, Package () { ^^I2C2.PMIC.OVTH })
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Name (_PR3, Package () { ^^I2C2.PMIC.OVTH })
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/* Port0 of CAM0 is connected to port0 of CIO2 device */
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Name (_DSD, Package () {
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ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
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@ -137,6 +506,9 @@ Scope (\_SB.PCI0.I2C2)
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0x00, ResourceConsumer, ,
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)
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})
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Name (_PR0, Package () { ^PMIC.VCMP })
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Name (_PR3, Package () { ^PMIC.VCMP })
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}
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}
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@ -154,13 +526,296 @@ Scope (\_SB.PCI0.I2C3)
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Return (0x0F)
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}
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/* Marks the availability of all the operation regions */
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Name (AVP2, Zero)
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Name (AVGP, Zero)
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Name (AVB0, Zero)
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Name (AVB1, Zero)
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Name (AVB2, Zero)
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Name (AVB3, Zero)
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Method (_REG, 2, NotSerialized)
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{
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If (LEqual (Arg0, 0x08))
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{
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/* Marks the availability of GeneralPurposeIO
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* 0x08: opregion space for GeneralPurposeIO
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*/
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Store (Arg1, AVGP)
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}
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If (LEqual (Arg0, 0xB0))
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{
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/* Marks the availability of
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* TI_PMIC_POWER_OPREGION_ID */
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Store (Arg1, AVB0)
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}
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If (LEqual (Arg0, 0xB1))
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{
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/* Marks the availability of
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* TI_PMIC_VR_VAL_OPREGION_ID */
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Store (Arg1, AVB1)
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}
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If (LEqual (Arg0, 0xB2))
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{
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/* Marks the availability of
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* TI_PMIC_CLK_OPREGION_ID */
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Store (Arg1, AVB2)
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}
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If (LEqual (Arg0, 0xB3))
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{
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/* Marks the availability of
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* TI_PMIC_CLK_FREQ_OPREGION_ID */
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Store (Arg1, AVB3)
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}
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If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1),
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LAnd(AVB2, AVB3))))
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{
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/* Marks the availability of all opregions */
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Store (1, AVP2)
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}
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Else
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{
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Store (0, AVP2)
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}
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}
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OperationRegion (GPOP, GeneralPurposeIo, 0, 0x2)
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Name (_CRS, ResourceTemplate ()
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{
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I2cSerialBus (0x0049, ControllerInitiated, 0x00061A80,
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AddressingMode7Bit, "\\_SB.PCI0.I2C3",
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0x00, ResourceConsumer, ,
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)
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/* GPIO.4 is AVDD pin for user facing camera */
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GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
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IoRestrictionOutputOnly, "\\_SB.PCI0.I2C3.PMIC",
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0x00, ResourceConsumer,,)
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{
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4
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}
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/* GPIO.5 is XSHUTDOWN pin for user facing camera */
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GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
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IoRestrictionOutputOnly, "\\_SB.PCI0.I2C3.PMIC",
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0x00, ResourceConsumer,,)
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{
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5
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}
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})
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/* PMIC operation regions */
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/* 0xB0: TI_PMIC_POWER_OPREGION_ID
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* VSIO: Sensor IO LDO output
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* VCMC: VCM LDO output
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* VAX1: Auxiliary LDO1 output
|
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* VAX2: Auxiliary LDO2 output
|
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* VACT: Analog LDO output
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* VDCT: Core buck output
|
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*/
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OperationRegion (PWR1, 0xB0, Zero, 0x0100)
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Field (PWR1, DWordAcc, NoLock, Preserve)
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{
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VSIO, 32,
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VCMC, 32,
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VAX1, 32,
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VAX2, 32,
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VACT, 32,
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VDCT, 32,
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}
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|
||||
/* 0xB1: TI_PMIC_VR_VAL_OPREGION_ID
|
||||
* SIOV: VSIO VR voltage value
|
||||
* IOVA: VIO VR voltage value
|
||||
* VCMV: VCM VR voltage value
|
||||
* AX1V: Auxiliary LDO1 VR voltage value
|
||||
* AX2V: Auxiliary LDO2 VR voltage value
|
||||
* ACVA: Analog LDO VR voltage
|
||||
* DCVA: Core buck VR volatage
|
||||
*/
|
||||
OperationRegion (PWR2, 0xB1, Zero, 0x0100)
|
||||
Field (PWR2, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
SIOV, 32,
|
||||
IOVA, 32,
|
||||
VCMV, 32,
|
||||
AX1V, 32,
|
||||
AX2V, 32,
|
||||
ACVA, 32,
|
||||
DCVA, 32,
|
||||
}
|
||||
|
||||
/* 0xB2: TI_PMIC_CLK_OPREGION_ID
|
||||
* PCTL: PLL control register
|
||||
* PCT2: PLL control 2 register
|
||||
* CFG1: Clock configuration 1 register
|
||||
* CFG2: Clock configuration 2 register
|
||||
*/
|
||||
OperationRegion (CLKC, 0xB2, Zero, 0x0100)
|
||||
Field (CLKC, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
PCTL, 32,
|
||||
PCT2, 32,
|
||||
CFG1, 32,
|
||||
CFG2, 32,
|
||||
}
|
||||
|
||||
/* 0xB3: TI_PMIC_CLK_FREQ_OPREGION_ID
|
||||
* PDV2: PLL output divider for HCLK_B
|
||||
* BODI: PLL output divider for boost clock
|
||||
* BUDI: PLL output divider for buck clock
|
||||
* PSWR: PLL reference clock setting
|
||||
* XTDV: Reference crystal divider
|
||||
* PLDV: PLL feedback divider
|
||||
* PODV: PLL output divider for HCLK_A
|
||||
*/
|
||||
OperationRegion (CLKF, 0xB3, Zero, 0x0100)
|
||||
Field (CLKF, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
PDV2, 32,
|
||||
BODI, 32,
|
||||
BUDI, 32,
|
||||
PSWR, 32,
|
||||
XTDV, 32,
|
||||
PLDV, 32,
|
||||
PODV, 32,
|
||||
}
|
||||
|
||||
Mutex (MUTC, 0)
|
||||
Method (CLKE, 0, Serialized) {
|
||||
/* save Acquire result so we can check for
|
||||
Mutex acquired */
|
||||
Store (Acquire (MUTC, 1000), Local0)
|
||||
/* check for Mutex acquired */
|
||||
If (LEqual (Local0, Zero)) {
|
||||
/* Set boost clock divider */
|
||||
BODI = 3
|
||||
/* Set buck clock divider */
|
||||
BUDI = 2
|
||||
/* Set the PLL_REF_CLK cyles */
|
||||
PSWR = 19
|
||||
/* Set the reference crystal divider */
|
||||
XTDV = 170
|
||||
/* Set PLL feedback divider */
|
||||
PLDV = 32
|
||||
/* Set PLL output divider for HCLK_A */
|
||||
PODV = 1
|
||||
/* Enable HCLK_A clock.
|
||||
* CFG1: output selection for HCLK_A.
|
||||
* CFG2: set drive strength for HCLK_A.
|
||||
*/
|
||||
CFG2 = 1
|
||||
CFG1 = 2
|
||||
/* Enable PLL output, crystal oscillator
|
||||
* input capacitance control and set
|
||||
* Xtal oscillator as clock source.
|
||||
*/
|
||||
PCTL = 209
|
||||
Sleep(1)
|
||||
Release (MUTC)
|
||||
}
|
||||
}
|
||||
|
||||
Method (CLKD, 0, Serialized) {
|
||||
/* save Acquire result so we can check for
|
||||
Mutex acquired */
|
||||
Store (Acquire (MUTC, 1000), Local0)
|
||||
/* check for Mutex acquired */
|
||||
If (LEqual (Local0, Zero)) {
|
||||
BODI = 0
|
||||
BUDI = 0
|
||||
PSWR = 0
|
||||
XTDV = 0
|
||||
PLDV = 0
|
||||
PODV = 0
|
||||
/* Disable HCLK_A clock */
|
||||
CFG2 = 0
|
||||
CFG1 = 0
|
||||
PCTL = 0
|
||||
Release (MUTC)
|
||||
}
|
||||
}
|
||||
|
||||
/* Reference count for VSIO */
|
||||
Mutex (MUTV, 0)
|
||||
Name (VSIC, 0)
|
||||
Method (DOVD, 1, Serialized) {
|
||||
/* Save Acquire result so we can check for
|
||||
Mutex acquired */
|
||||
Store (Acquire (MUTV, 1000), Local0)
|
||||
/* Check for Mutex acquired */
|
||||
If (LEqual (Local0, Zero)) {
|
||||
/* Turn off VSIO */
|
||||
If (LEqual (Arg0, Zero)) {
|
||||
VSIO = 0
|
||||
} ElseIf (LEqual (Arg0, 1)) {
|
||||
VSIO = 3
|
||||
}
|
||||
Release (MUTV)
|
||||
}
|
||||
}
|
||||
|
||||
/* Power resource methods for CAM1 */
|
||||
PowerResource (OVFI, 0, 0) {
|
||||
Name (STA, 0)
|
||||
Method (_ON, 0, Serialized) {
|
||||
If (LEqual (AVP2, 1)) {
|
||||
If (LEqual (STA, 0)) {
|
||||
/* Enable VSIO regulator +
|
||||
daisy chain */
|
||||
DOVD(1)
|
||||
|
||||
VAX2 = 1 /* Enable VAUX2 */
|
||||
|
||||
if (LNotEqual (AX2V, 52)) {
|
||||
/* Set VAUX2 as
|
||||
1.8006 V */
|
||||
AX2V = 52
|
||||
}
|
||||
Sleep(1)
|
||||
|
||||
\_SB.PCI0.I2C3.PMIC.CLKE()
|
||||
|
||||
VAX1 = 1 /* Enable VAUX1 */
|
||||
if (LNotEqual (AX1V, 19)) {
|
||||
/* Set VAUX1 as 1.2132V */
|
||||
AX1V = 19
|
||||
}
|
||||
Sleep(3)
|
||||
|
||||
\_SB.PCI0.I2C3.CAM1.CGP4(1)
|
||||
Sleep(3)
|
||||
|
||||
\_SB.PCI0.I2C3.CAM1.CGP5(1)
|
||||
Sleep(5)
|
||||
STA = 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Method (_OFF, 0, Serialized) {
|
||||
If (LEqual (AVP2, 1)) {
|
||||
If (LEqual (STA, 1)) {
|
||||
Sleep(2)
|
||||
\_SB.PCI0.I2C3.PMIC.CLKD()
|
||||
Sleep(2)
|
||||
\_SB.PCI0.I2C3.CAM1.CGP5(0)
|
||||
Sleep(3)
|
||||
VAX1 = 0
|
||||
Sleep(1)
|
||||
\_SB.PCI0.I2C3.CAM1.CGP4(0)
|
||||
Sleep(1)
|
||||
VAX2 = 0
|
||||
Sleep(1)
|
||||
DOVD(0)
|
||||
Sleep(1)
|
||||
|
||||
}
|
||||
STA = 0
|
||||
}
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized) {
|
||||
Return (STA)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (CAM1)
|
||||
|
|
@ -184,6 +839,47 @@ Scope (\_SB.PCI0.I2C3)
|
|||
)
|
||||
})
|
||||
|
||||
Field (\_SB.PCI0.I2C3.PMIC.GPOP, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Connection
|
||||
(
|
||||
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
|
||||
IoRestrictionOutputOnly,
|
||||
"\\_SB.PCI0.I2C3.PMIC", 0x00,
|
||||
ResourceConsumer,,)
|
||||
{
|
||||
4
|
||||
}
|
||||
),
|
||||
GPO4, 1,
|
||||
Connection
|
||||
(
|
||||
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
|
||||
IoRestrictionOutputOnly,
|
||||
"\\_SB.PCI0.I2C3.PMIC", 0x00,
|
||||
ResourceConsumer,,)
|
||||
{
|
||||
5
|
||||
}
|
||||
),
|
||||
GPO5, 1,
|
||||
}
|
||||
|
||||
/* Set or clear GPO4 GPIO */
|
||||
Method (CGP4, 1, Serialized)
|
||||
{
|
||||
GPO4 = Arg0
|
||||
}
|
||||
|
||||
/* Set or clear GPO5 GPIO */
|
||||
Method (CGP5, 1, Serialized)
|
||||
{
|
||||
GPO5 = Arg0
|
||||
}
|
||||
|
||||
Name (_PR0, Package () { ^^I2C3.PMIC.OVFI })
|
||||
Name (_PR3, Package () { ^^I2C3.PMIC.OVFI })
|
||||
|
||||
/* Port0 of CAM1 is connected to port1 of CIO2 device */
|
||||
Name (_DSD, Package () {
|
||||
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
|
||||
|
|
|
|||
Loading…
Reference in New Issue