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Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupport 

(1) Wifi is connected on RP1 which is 1c.0 , so enabling
    1c.0 and disabling 1d.0
(2) kepler is on RP5 which is 1c.4, so enabling it
(3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can
    get enabled.

BRANCH=None
BUG=chrome-os-partner:43738
TEST=Built and boot for Kunimitsu. checked all PCIe powersaving
     states (LTR, L1, L1S) are enabled

Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293482
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/11237
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Pratik Prajapati 2015-08-13 15:21:37 -07:00 committed by Aaron Durbin
parent 4938426783
commit f1acb9b69d
1 changed files with 5 additions and 3 deletions
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8
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -33,6 +33,8 @@ chip soc/intel/skylake
register "PcieRpEnable[4]" = "1" register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2" register "PcieRpClkReqNumber[4]" = "2"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
# GPE configuration # GPE configuration
register "gpe0_en_1" = "0x00000000" register "gpe0_en_1" = "0x00000000"
@ -106,15 +108,15 @@ chip soc/intel/skylake
device pci 19.0 on end # UART Controller #2 device pci 19.0 on end # UART Controller #2
device pci 19.1 on end # I2C Controller #5 device pci 19.1 on end # I2C Controller #5
device pci 19.2 on end # I2C Controller #4 device pci 19.2 on end # I2C Controller #4
device pci 1c.0 off end # PCI Express Port 1 device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2 device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3 device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4 device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5 device pci 1c.4 on end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6 device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7 device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8 device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9 device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10 device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11 device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12 device pci 1d.3 off end # PCI Express Port 12