From f1b11e7fcc36d1e9023aba642796dc924cb35288 Mon Sep 17 00:00:00 2001 From: Usha P Date: Tue, 18 Jan 2022 13:37:15 +0530 Subject: [PATCH] soc/intel/alderlake: Add GPIO Controller device ID for ADL-N Add PCH ACPI Device ID for Alder Lake N SOC GPIO Controller. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P Change-Id: I6eb15751dd303b4b445cb64f25a040302e50c09d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61172 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Maulik V Vaghela --- src/soc/intel/alderlake/include/soc/gpio.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h index acaade449d..407c3b757f 100644 --- a/src/soc/intel/alderlake/include/soc/gpio.h +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -6,8 +6,13 @@ #include #include +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define CROS_GPIO_NAME "INTC1057" +#define CROS_GPIO_DEVICE_NAME "INTC1057:00" +#else #define CROS_GPIO_NAME "INTC1055" #define CROS_GPIO_DEVICE_NAME "INTC1055:00" +#endif /* Enable GPIO community power management configuration */ #define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \