soc/amd/genoa: Add opensil MPIO chip files
Add the openSIL MPIO chip driver that allows specifying the MPIO lane configuration in the mainboard's devicetree instead of having this configuration in a separate port descriptor C file. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1d408a7eff22423612bc5eb9bfebaf0d86642829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76520 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
Felix Held
parent
62389ab04a
commit
f1b1412068
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## SPDX-License-Identifier: GPL-2.0-only
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subdirs-y += mpio
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CPPFLAGS_ramstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF
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CPPFLAGS_romstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF
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## SPDX-License-Identifier: GPL-2.0-only
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ramstage-y += chip.c
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$(obj)/ramstage/vendorcode/amd/opensil/genoa_poc/mpio/chip.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <RcMgr/DfX/RcManager4-api.h>
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#include <NBIO/NbioClass-api.h>
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#include <Mpio/MpioClass-api.h>
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#include <Mpio/Common/MpioStructs.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include "chip.h"
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static void nbio_config(void)
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{
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NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
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NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
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input->CfgHdAudioEnable = false;
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input->EsmEnableAllRootPorts = false;
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input->EsmTargetSpeed = 16;
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input->CfgRxMarginPersistenceMode = 1;
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input->CfgDxioFrequencyVetting = false;
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input->CfgSkipPspMessage = 1;
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input->CfgEarlyTrainTwoPcieLinks = false;
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input->EarlyBmcLinkTraining = true;
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input->EdpcEnable = 0;
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input->PcieAerReportMechanism = 2;
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input->SevSnpSupport = false;
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}
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static void mpio_global_config(MPIOCLASS_INPUT_BLK *mpio_data)
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{
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mpio_data->CfgDxioClockGating = 1;
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mpio_data->PcieDxioTimingControlEnable = 0;
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mpio_data->PCIELinkReceiverDetectionPolling = 0;
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mpio_data->PCIELinkResetToTrainingTime = 0;
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mpio_data->PCIELinkL0Polling = 0;
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mpio_data->PCIeExactMatchEnable = 0;
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mpio_data->DxioPhyValid = 1;
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mpio_data->DxioPhyProgramming = 1;
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mpio_data->CfgSkipPspMessage = 1;
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mpio_data->DxioSaveRestoreModes = 0xff;
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mpio_data->AmdAllowCompliance = 0;
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mpio_data->AmdAllowCompliance = 0xff;
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mpio_data->SrisEnableMode = 0xff;
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mpio_data->SrisSkipInterval = 0;
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mpio_data->SrisSkpIntervalSel = 1;
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mpio_data->SrisCfgType = 0;
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mpio_data->SrisAutoDetectMode = 0xff;
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mpio_data->SrisAutodetectFactor = 0;
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mpio_data->SrisLowerSkpOsGenSup = 0;
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mpio_data->SrisLowerSkpOsRcvSup = 0;
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mpio_data->AmdCxlOnAllPorts = 1;
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mpio_data->CxlCorrectableErrorLogging = 1;
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mpio_data->CxlUnCorrectableErrorLogging = 1;
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// This is also available in Nbio. How to handle duplicate entries?
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mpio_data->CfgAEREnable = 1;
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mpio_data->CfgMcCapEnable = 0;
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mpio_data->CfgRcvErrEnable = 0;
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mpio_data->EarlyBmcLinkTraining = 1;
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mpio_data->SurpriseDownFeature = 1;
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mpio_data->LcMultAutoSpdChgOnLastRateEnable = 0;
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mpio_data->AmdRxMarginEnabled = 1;
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mpio_data->CfgPcieCVTestWA = 1;
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mpio_data->CfgPcieAriSupport = 1;
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mpio_data->CfgNbioCTOtoSC = 0;
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mpio_data->CfgNbioCTOIgnoreError = 1;
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mpio_data->CfgNbioSsid = 0;
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mpio_data->CfgIommuSsid = 0;
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mpio_data->CfgPspccpSsid = 0;
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mpio_data->CfgNtbccpSsid = 0;
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mpio_data->CfgNbifF0Ssid = 0;
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mpio_data->CfgNtbSsid = 0;
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mpio_data->AmdPcieSubsystemDeviceID = 0x1453;
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mpio_data->AmdPcieSubsystemVendorID = 0x1022;
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mpio_data->GppAtomicOps = 1;
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mpio_data->GfxAtomicOps = 1;
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mpio_data->AmdNbioReportEdbErrors = 0;
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mpio_data->OpnSpare = 0;
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mpio_data->AmdPreSilCtrl0 = 0;
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mpio_data->MPIOAncDataSupport = 1;
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mpio_data->AfterResetDelay = 0;
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mpio_data->CfgEarlyLink = 0;
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mpio_data->AmdCfgExposeUnusedPciePorts = 1; // Show all ports
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mpio_data->CfgForcePcieGenSpeed = 0;
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mpio_data->CfgSataPhyTuning = 0;
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mpio_data->PcieLinkComplianceModeAllPorts = 0;
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mpio_data->AmdMCTPEnable = 0;
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mpio_data->SbrBrokenLaneAvoidanceSup = 1;
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mpio_data->AutoFullMarginSup = 1;
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// A getter and setter, both are needed for this PCD.
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mpio_data->AmdPciePresetMask8GtAllPort = 0xffffffff;
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// A getter and setter, both are needed for this PCD.
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mpio_data->AmdPciePresetMask16GtAllPort = 0xffffffff;
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// A getter and setter, both are needed for this PCD.
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mpio_data->AmdPciePresetMask32GtAllPort = 0xffffffff;
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mpio_data->PcieLinkAspmAllPort = 0xff;
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mpio_data->SyncHeaderByPass = 1;
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mpio_data->CxlTempGen5AdvertAltPtcl = 0;
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/* TODO handle this differently on multisocket */
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mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST;
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mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList;
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}
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static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
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{
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DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager, 0);
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rc_mgr_input_block->BmcSocket = socket;
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rc_mgr_input_block->EarlyBmcLinkLaneNum = lane;
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NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
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NBIOCLASS_INPUT_BLK *nbio_input = &nbio_data->NbioInputBlk;
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nbio_input->EarlyBmcLinkSocket = socket;
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nbio_input->EarlyBmcLinkLaneNum = lane;
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nbio_input->EarlyBmcLinkDie = 0;
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MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
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mpio_data->EarlyBmcLinkSocket = socket;
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mpio_data->EarlyBmcLinkLaneNum = lane;
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mpio_data->EarlyBmcLinkDie = 0;
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}
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static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev,
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struct vendorcode_amd_opensil_genoa_poc_mpio_config *const config)
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{
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static uint32_t slot_num;
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const uint32_t domain = dev->bus->dev->path.domain.domain;
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const uint32_t devfn = dev->path.pci.devfn;
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printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n",
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domain, PCI_SLOT(devfn), PCI_FUNC(devfn));
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if (config->bmc) {
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setup_bmc_lanes(config->start_lane, 0); // TODO support multiple sockets
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return;
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}
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static int mpio_port = 0;
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MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST };
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if (config->type == PCIE) {
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const MPIO_ENGINE_DATA engine_data =
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MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine,
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config->start_lane, config->end_lane,
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config->hotplug == HotplugDisabled ? 0 : 1,
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config->gpio_group);
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port.EngineData = engine_data;
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const MPIO_PORT_DATA port_data =
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MPIO_PORT_DATA_INITIALIZER_PCIE(MpioPortEnabled,
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PCI_SLOT(devfn),
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PCI_FUNC(devfn),
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config->hotplug,
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config->speed,
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0, // No backup PCIe speed
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config->aspm,
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config->aspm_l1_1,
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config->aspm_l1_2,
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config->clock_pm);
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port.Port = port_data;
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} else if (config->type == SATA) {
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const MPIO_ENGINE_DATA engine_data =
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MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine,
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config->start_lane, config->end_lane,
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0, // meaningless field
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config->gpio_group);
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port.EngineData = engine_data;
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const MPIO_PORT_DATA port_data = { .PortPresent = 1 };
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port.Port = port_data;
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}
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port.Port.AlwaysExpose = 1;
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port.Port.SlotNum = ++slot_num;
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mpio_data->PcieTopologyData.PortList[mpio_port] = port;
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/* Update TERMINATE list */
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if (mpio_port > 0)
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mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0;
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mpio_port++;
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}
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static void mpio_config(void *const config)
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{
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MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
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mpio_global_config(mpio_data);
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nbio_config();
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/* Find all devices with this chip */
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for (struct device *dev = &dev_root; dev; dev = dev->next)
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if (dev->chip_ops->init == mpio_config)
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per_device_config(mpio_data, dev->bus->dev, dev->chip_info);
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}
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struct chip_operations vendorcode_amd_opensil_genoa_poc_mpio_ops = {
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CHIP_NAME("AMD GENOA MPIO")
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.init = mpio_config,
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};
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@ -0,0 +1,65 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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/*
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* GENOA MPIO mapping
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* P0 -> [0-15]
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* G0 -> [16-31]
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* P1 -> [32-47]
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* G1 -> [48-63]
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* P2 -> [64-79]
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* G2 -> [80-95]
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* P3 -> [96-111]
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* G3 -> [112-127]
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* P4 -> [128-131]
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* P5 -> [132-136]
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*/
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enum mpio_type {
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PCIE,
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SATA,
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};
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/* Sync with PCIE_HOTPLUG_TYPE */
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enum mpio_hotplug {
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HotplugDisabled, ///< Hotplug disable
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Basic, ///< Basic Hotplug
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ServerExpress, ///< Server Hotplug Express Module
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Enhanced, ///< Enhanced
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Inboard, ///< Inboard
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ServerEntSSD, ///< Server Hotplug Enterprise SSD
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UBM, ///< UBM Backplane
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OCP, ///< OCP NIC 3.0
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};
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enum pcie_link_speed {
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MaxSupported,
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Gen1,
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Gen2,
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Gen3,
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Gen4,
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Gen5,
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};
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/* Sync with PCIE_ASPM_TYPE */
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enum pcie_asmp {
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aspm_disabled,
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L0s,
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L1,
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L0sL1,
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};
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struct vendorcode_amd_opensil_genoa_poc_mpio_config {
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enum mpio_type type;
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uint8_t start_lane;
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uint8_t end_lane;
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uint8_t gpio_group;
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enum mpio_hotplug hotplug;
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enum pcie_link_speed speed;
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enum pcie_asmp aspm;
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uint8_t aspm_l1_1 : 1;
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uint8_t aspm_l1_2 : 1;
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uint8_t clock_pm : 1;
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uint8_t bmc : 1;
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};
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