intel/fsp: Update cannonlake fsp header
Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: 1. Add PeciSxRest option. 2. Add Thermal Velocity Boost option. 3. Add VR power deliver design option. 4. Match MrcChannelSts. TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Reviewed-on: https://review.coreboot.org/23677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao
Martin Roth
parent
2242919177
commit
f1b1d92854
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@ -40,13 +40,6 @@ static struct chipset_power_state power_state CAR_GLOBAL;
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0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
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}
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/* Memory Channel Present Status */
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enum {
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CHANNEL_NOT_PRESENT,
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CHANNEL_DISABLED,
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CHANNEL_PRESENT
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};
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/* Save the DIMM information for SMBIOS table 17 */
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static void save_dimm_info(void)
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{
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@ -474,9 +474,21 @@ typedef struct {
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**/
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UINT8 CpuTraceHubMemReg1Size;
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/** Offset 0x00F6
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/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command
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Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace3[6];
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UINT8 PeciC10Reset;
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/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command
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Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
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$EN_DIS
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**/
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UINT8 PeciSxReset;
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/** Offset 0x00F8
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**/
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UINT8 UnusedUpdSpace3[4];
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/** Offset 0x00FC - Enable Intel HD Audio (Azalia)
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0: Disable, 1: Enable (Default) Azalia controller
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@ -691,9 +703,24 @@ typedef struct {
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**/
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UINT8 DmiGen3RxCtlePeaking[4];
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/** Offset 0x0144
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/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping
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0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
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caused by high package temperatures for processors that implement the Intel Thermal
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Velocity Boost (TVB) feature
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0: Disabled, 1: Enabled
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**/
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UINT8 UnusedUpdSpace6[4];
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UINT8 TvbRatioClipping;
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/** Offset 0x0145 - Thermal Velocity Boost voltage optimization
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0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
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for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
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0: Disabled, 1: Enabled
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**/
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UINT8 TvbVoltageOptimization;
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/** Offset 0x0146
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**/
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UINT8 UnusedUpdSpace6[2];
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/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
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Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
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@ -1374,8 +1401,8 @@ typedef struct {
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**/
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UINT8 PchSmbAlertEnable;
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/** Offset 0x0463 - ReservedSecurityPreMem
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Reserved for Security Pre-Mem
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/** Offset 0x0463 - ReservedPchPreMem
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Reserved for Pch Pre-Mem
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$EN_DIS
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**/
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UINT8 ReservedPchPreMem[13];
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@ -2428,7 +2455,7 @@ typedef struct {
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**/
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UINT8 Gen3SwEqEnableVocTest;
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/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode
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/** Offset 0x0537 - PCIe Rx Compliance Testing Mode
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Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
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PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
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it should only be set when doing PCIe compliance testing
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@ -2522,7 +2549,7 @@ typedef struct {
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/** Offset 0x0583 - BdatTestType
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Indicates the type of Memory Training data to populate into the BDAT ACPI table.
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0:Rank Marign Tool, 1:Margin2D
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0:Rank Margin Tool, 1:Margin2D
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**/
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UINT8 BdatTestType;
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@ -2542,11 +2569,17 @@ typedef struct {
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**/
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UINT16 BiosSize;
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/** Offset 0x0594 - SecurityTestRsvd
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/** Offset 0x0594 - TxtAcheckRequest
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Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
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$EN_DIS
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**/
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UINT8 TxtAcheckRequest;
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/** Offset 0x0595 - SecurityTestRsvd
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Reserved for SA Pre-Mem Test
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$EN_DIS
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**/
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UINT8 SecurityTestRsvd[4];
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UINT8 SecurityTestRsvd[3];
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/** Offset 0x0598 - Smbus dynamic power gating
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Disable or Enable Smbus dynamic power gating.
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@ -1093,15 +1093,22 @@ typedef struct {
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**/
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UINT16 ImonSlope1[5];
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/** Offset 0x0324 - ReservedCpuPostMemProduction
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/** Offset 0x0324 - CPU VR Power Delivery Design
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Used to communicate the power delivery design capability of the board. This value
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is an enum of the available power delivery segments that are defined in the Platform
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Design Guide.
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**/
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UINT32 VrPowerDeliveryDesign;
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/** Offset 0x0328 - ReservedCpuPostMemProduction
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Reserved for CPU Post-Mem Production
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$EN_DIS
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**/
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UINT8 ReservedCpuPostMemProduction[1];
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/** Offset 0x0325
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/** Offset 0x0329
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**/
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UINT8 UnusedUpdSpace10[33];
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UINT8 UnusedUpdSpace10[29];
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/** Offset 0x0346 - Enable DMI ASPM
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Deprecated.
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@ -1869,7 +1876,6 @@ typedef struct {
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0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
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pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
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for I2C1, and so on.
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0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU
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**/
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UINT8 PchSerialIoI2cPadsTermination[6];
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@ -2283,7 +2289,7 @@ typedef struct {
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**/
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UINT8 ChapDeviceEnable;
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/** Offset 0x07B2 - Skip PAM regsiter lock
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/** Offset 0x07B2 - Skip PAM register lock
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Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
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PAM registers will be locked by RC
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$EN_DIS
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@ -2830,9 +2836,10 @@ typedef struct {
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**/
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UINT16 PsysPmax;
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/** Offset 0x0858
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/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
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Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
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**/
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UINT8 Reserved0[2];
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UINT16 CstateLatencyControl0Irtl;
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/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
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Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
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@ -3074,8 +3081,7 @@ typedef struct {
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UINT8 PchUnlockGpioPads;
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/** Offset 0x08C2 - PCH Unlock SBI access
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This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1:
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Unlock SBI access.
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Deprecated
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$EN_DIS
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**/
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UINT8 PchSbiUnlock;
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@ -0,0 +1,136 @@
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/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp T Core UPD
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**/
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typedef struct {
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/** Offset 0x0020
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x0024
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0028
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**/
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UINT32 CodeRegionBase;
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/** Offset 0x002C
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**/
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UINT32 CodeRegionSize;
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/** Offset 0x0030
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**/
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UINT8 Reserved[16];
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} FSPT_CORE_UPD;
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/** Fsp T Configuration
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**/
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typedef struct {
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/** Offset 0x0040 - PcdSerialIoUartDebugEnable
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Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIoUartDebugEnable;
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/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
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Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
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Core interface, it cannot be used for debug purpose.
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIoUartNumber;
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/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT
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Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is
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set to UART0.
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0:default pins, 1:pins muxed with CNV_BRI/RGI
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**/
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UINT8 PcdSerialIoUart0PinMuxing;
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/** Offset 0x0043
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**/
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UINT8 UnusedUpdSpace0;
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/** Offset 0x0044
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**/
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UINT32 PcdSerialIoUartInputClock;
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/** Offset 0x0048 - Pci Express Base Address
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Base address to be programmed for Pci Express
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**/
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UINT64 PcdPciExpressBaseAddress;
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/** Offset 0x0050 - Pci Express Region Length
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Region Length to be programmed for Pci Express
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**/
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UINT32 PcdPciExpressRegionLength;
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/** Offset 0x0054
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**/
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UINT8 ReservedFsptUpd1[44];
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} FSP_T_CONFIG;
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/** Fsp T UPD Configuration
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**/
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typedef struct {
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/** Offset 0x0000
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**/
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FSP_UPD_HEADER FspUpdHeader;
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/** Offset 0x0020
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**/
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FSPT_CORE_UPD FsptCoreUpd;
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/** Offset 0x0040
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**/
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FSP_T_CONFIG FsptConfig;
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/** Offset 0x0080
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**/
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UINT16 UpdTerminator;
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} FSPT_UPD;
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#pragma pack()
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#endif
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@ -83,6 +83,19 @@ typedef struct {
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UINT8 Build; ///< Build number
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} SiMrcVersion;
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//
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// Matches MrcChannelSts enum in MRC
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//
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#ifndef CHANNEL_NOT_PRESENT
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#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
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#endif
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#ifndef CHANNEL_DISABLED
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#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
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#endif
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#ifndef CHANNEL_PRESENT
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#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
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#endif
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//
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// Matches MrcDimmSts enum in MRC
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//
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