device/pci: Fix PCI accessor headers

PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/arch/x86/include/arch/io.h

@@ -203,10 +203,6 @@ static __always_inline void write64(volatile void *addr,
 }
 #endif
 
-/* FIXME: We should avoid this indirect include. Also this has to
- * appear here after all MMIO and IO read/write functions. */
-#include <arch/pci_ops.h>
-
 #ifdef __SIMPLE_DEVICE__
 
 #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))

src/commonlib/storage/pci_sdhci.c

@@ -21,6 +21,7 @@
 #include <assert.h>
 #include <commonlib/sdhci.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "sd_mmc.h"
 #include <stdint.h>
 #include "storage.h"

src/cpu/amd/family_10h-family_15h/init_cpus.c

@@ -15,6 +15,7 @@
  */
 
 #include <cpu/amd/msr.h>
+#include <device/pci_ops.h>
 #include "init_cpus.h"
 
 #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)

src/cpu/amd/family_10h-family_15h/model_10xxx_init.c

@@ -21,6 +21,7 @@
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <cpu/x86/smm.h>
 #include <cpu/x86/pae.h>

src/cpu/amd/family_10h-family_15h/monotonic_timer.c

@@ -19,6 +19,7 @@
 #include <cpu/amd/msr.h>
 #include <timer.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <northbridge/amd/amdht/AsPsDefs.h>
 
 static struct monotonic_counter {

src/cpu/amd/family_10h-family_15h/powernow_acpi.c

@@ -23,6 +23,7 @@
 #include <arch/acpigen.h>
 #include <cpu/amd/powernow.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdfam10_sysconf.h>
 #include <arch/cpu.h>

src/cpu/amd/family_10h-family_15h/ram_calc.c

@@ -19,6 +19,7 @@
 #include <cpu/amd/mtrr.h>
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci.h>
 

src/cpu/amd/quadcore/amd_sibling.c

@@ -17,6 +17,7 @@
 #include <cpu/x86/lapic.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 #include <smp/spinlock.h>
 #include <cpu/x86/mtrr.h>

src/cpu/amd/quadcore/quadcore.c

@@ -17,6 +17,7 @@
 
 #include <arch/cpu.h>
 #include <console/console.h>
+#include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
 #include "option_table.h"

src/cpu/amd/quadcore/quadcore_id.c

@@ -18,6 +18,7 @@
 
 #include <arch/cpu.h>
 #include <cpu/amd/multicore.h>
+#include <device/pci_ops.h>
 #ifdef __PRE_RAM__
 #include <cpu/amd/msr.h>
 #endif

src/cpu/intel/fsp_model_406dx/bootblock.c

@@ -20,6 +20,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <reset.h>
 #include <southbridge/intel/fsp_rangeley/soc.h>
 

src/device/cardbus_device.c

@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/cardbus.h>
 

src/device/hypertransport.c

@@ -24,6 +24,7 @@
 #include <device/device.h>
 #include <device/path.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/hypertransport.h>
 

src/device/pci_class.c

@@ -16,6 +16,7 @@
 
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
 #include <stdlib.h>

src/device/pci_device.c

@@ -33,6 +33,7 @@
 
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <bootmode.h>
 #include <console/console.h>
 #include <stdlib.h>

src/device/pcix_device.c

@@ -17,6 +17,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pcix.h>
 
 static void pcix_tune_dev(struct device *dev)

src/drivers/dec/21143/21143.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
 

src/drivers/generic/bayhub/bh720.c

@@ -19,6 +19,7 @@
 #include <device/device.h>
 #include <device/path.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include "chip.h"
 #include "bh720.h"

src/drivers/intel/gma/vbt.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <delay.h>
 #include <device/device.h>
 #include <string.h>

src/drivers/intel/wifi/wifi.c

@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <elog.h>
 #include <sar.h>

src/drivers/net/atl1e.c

@@ -25,6 +25,7 @@
 #include <string.h>
 #include <console/console.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 
 #define REG_SPI_FLASH_CTRL		0x200
 #define SPI_FLASH_CTRL_EN_VPD		0x2000

src/drivers/ricoh/rce822/rce822.c

@@ -18,6 +18,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include "chip.h"
 
 static void rce822_enable(struct device *dev)

src/drivers/uart/oxpcie.c

@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <console/uart.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 static void oxford_oxpcie_enable(struct device *dev)
 {

src/drivers/uart/oxpcie_early.c

@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/early_variables.h>
 #include <boot/coreboot_tables.h>
 #include <console/uart.h>

src/drivers/usb/pci_ehci.c

@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <device/pci_ehci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <string.h>

src/include/device/pci.h

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <device/resource.h>
 #include <device/device.h>
-#include <device/pci_ops.h>
 #include <device/pci_rom.h>
 
 

src/include/device/pci_ops.h

@@ -12,7 +12,7 @@ u32 pci_read_config32(struct device *dev, unsigned int where);
 void pci_write_config8(struct device *dev, unsigned int where, u8 val);
 void pci_write_config16(struct device *dev, unsigned int where, u16 val);
 void pci_write_config32(struct device *dev, unsigned int where, u32 val);
-
+const struct pci_bus_operations *pci_bus_default_ops(struct device *dev);
 #endif
 
 #ifdef __SIMPLE_DEVICE__
@@ -99,6 +99,4 @@ void pci_update_config32(struct device *dev, int reg, u32 mask, u32 or)
 	pci_write_config32(dev, reg, reg32);
 }
 
-const struct pci_bus_operations *pci_bus_default_ops(struct device *dev);
-
 #endif /* PCI_OPS_H */

src/lib/reg_script.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>

src/mainboard/adi/rcc-dff/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>

src/mainboard/advansus/a785e-i/romstage.c

@@ -19,6 +19,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <timestamp.h>

src/mainboard/amd/bimini_fam10/romstage.c

@@ -19,6 +19,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/mahogany_fam10/mainboard.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>

src/mainboard/amd/mahogany_fam10/mptable.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/amd/olivehill/romstage.c

@@ -17,6 +17,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <commonlib/loglevel.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>

src/mainboard/amd/parmer/romstage.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c

@@ -15,6 +15,7 @@
 
 #include <console/console.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/multicore.h>

src/mainboard/amd/thatcher/romstage.c

@@ -18,6 +18,7 @@
 #include <device/pci_def.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <commonlib/loglevel.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>

src/mainboard/amd/tilapia_fam10/mainboard.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>

src/mainboard/amd/tilapia_fam10/mptable.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/aopen/dxplplusu/fadt.c

@@ -15,6 +15,7 @@
 
 #include <string.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <version.h>
 

src/mainboard/apple/macbook21/romstage.c

@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/lapic.h>

src/mainboard/apple/macbookair4_2/romstage.c

@@ -15,6 +15,7 @@
 #include <string.h>
 #include <arch/byteorder.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>

src/mainboard/asrock/b75pro3-m/romstage.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <superio/nuvoton/nct6776/nct6776.h>
 #include <superio/nuvoton/common/nuvoton.h>

src/mainboard/asrock/g41c-gs/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/bist.h>

src/mainboard/asrock/imb-a180/romstage.c

@@ -18,6 +18,7 @@
 #include <device/pci_def.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <commonlib/loglevel.h>
 
 #include <northbridge/amd/agesa/state_machine.h>

src/mainboard/asus/am1i-a/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <commonlib/loglevel.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/common/amd_defs.h>

src/mainboard/asus/f2a85-m/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/common/amd_defs.h>

src/mainboard/asus/h61m-cs/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <northbridge/intel/sandybridge/sandybridge.h>
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <superio/nuvoton/common/nuvoton.h>

src/mainboard/asus/kcma-d8/acpi_tables.c

@@ -18,6 +18,7 @@
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <cpu/amd/amdfam10_sysconf.h>
 
 unsigned long acpi_fill_madt(unsigned long current)

src/mainboard/asus/kcma-d8/bootblock.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 
 void bootblock_mainboard_init(void)

src/mainboard/asus/kcma-d8/mainboard.c

@@ -18,6 +18,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>

src/mainboard/asus/kcma-d8/mptable.c

@@ -17,6 +17,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/asus/kcma-d8/romstage.c

@@ -21,6 +21,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/kfsn4-dre/acpi_tables.c

@@ -24,6 +24,7 @@
 #include <assert.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/asus/kfsn4-dre/get_bus_conf.c

@@ -20,6 +20,7 @@
 
 #include <console/console.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>

src/mainboard/asus/kfsn4-dre/mptable.c

@@ -24,6 +24,7 @@
 
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/asus/kfsn4-dre/romstage.c

@@ -22,6 +22,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/kgpe-d16/acpi_tables.c

@@ -18,6 +18,7 @@
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <cpu/amd/amdfam10_sysconf.h>
 
 unsigned long acpi_fill_madt(unsigned long current)

src/mainboard/asus/kgpe-d16/bootblock.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 
 void bootblock_mainboard_init(void)

src/mainboard/asus/kgpe-d16/mainboard.c

@@ -18,6 +18,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>

src/mainboard/asus/kgpe-d16/mptable.c

@@ -17,6 +17,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/asus/kgpe-d16/romstage.c

@@ -21,6 +21,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/m4a78-em/mainboard.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>

src/mainboard/asus/m4a78-em/mptable.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/asus/m4a785-m/mainboard.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>

src/mainboard/asus/m4a785-m/mptable.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/asus/m5a88-v/romstage.c

@@ -21,6 +21,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/p5gc-mx/romstage.c

@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>

src/mainboard/asus/p5qc/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <southbridge/intel/i82801jx/i82801jx.h>
 #include <southbridge/intel/common/gpio.h>

src/mainboard/asus/p5qpl-am/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/intel/speedstep.h>

src/mainboard/asus/p8h61-m_pro/romstage.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>

src/mainboard/avalue/eax-785e/romstage.c

@@ -19,6 +19,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/bap/ode_e20XX/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
 #include <northbridge/amd/agesa/state_machine.h>

src/mainboard/biostar/a68n_5200/romstage.c

@@ -19,6 +19,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <commonlib/loglevel.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>

src/mainboard/biostar/am1ml/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <commonlib/loglevel.h>
 #include <northbridge/amd/agesa/state_machine.h>

src/mainboard/compulab/intense_pc/romstage.c

@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <superio/smsc/sio1007/chip.h>
 

src/mainboard/emulation/qemu-i440fx/northbridge.c

@@ -15,6 +15,7 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/lapic_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <stdint.h>
 #include <device/device.h>

src/mainboard/emulation/qemu-q35/acpi_tables.c

@@ -21,6 +21,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <version.h>
 
 #include "../qemu-i440fx/fw_cfg.h"

src/mainboard/emulation/qemu-q35/bootblock.c

@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <bootblock_common.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
 

src/mainboard/foxconn/d41s/romstage.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <superio/ite/common/ite.h>

src/mainboard/foxconn/g41s-k/romstage.c

@@ -18,6 +18,7 @@
 
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
+#include <device/pci_ops.h>
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>

src/mainboard/getac/p470/mainboard.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <delay.h>
 #include <drivers/intel/gma/int15.h>
 

src/mainboard/getac/p470/romstage.c

@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>

src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c

@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>

src/mainboard/gigabyte/ga-b75m-d3h/romstage.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>

src/mainboard/gigabyte/ga-b75m-d3v/romstage.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>

src/mainboard/gigabyte/ga-g41m-es2l/romstage.c

@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>

src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>

src/mainboard/gigabyte/ma785gm/mainboard.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>

src/mainboard/gigabyte/ma785gm/mptable.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/gigabyte/ma785gmt/mainboard.c

@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>

src/mainboard/gigabyte/ma785gmt/mptable.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/gigabyte/ma78gm/mainboard.c

@@ -18,6 +18,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>

src/mainboard/gigabyte/ma78gm/mptable.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>

src/mainboard/gizmosphere/gizmo2/romstage.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/google/auron/variants/buddy/variant.c

@@ -16,6 +16,7 @@
 #include <types.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>

src/mainboard/google/beltino/chromeos.c

@@ -15,6 +15,7 @@
 
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <bootmode.h>
 #include <device/device.h>
 #include <device/pci.h>

src/mainboard/google/beltino/lan.c

@@ -17,6 +17,7 @@
 #include <string.h>
 #include <types.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>

src/mainboard/google/butterfly/chromeos.c

@@ -17,6 +17,7 @@
 #include <string.h>
 #include <bootmode.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci.h>
 

src/mainboard/google/butterfly/romstage.c

@@ -18,6 +18,7 @@
 #include <string.h>
 #include <timestamp.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>