diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index f5d5dd1597..fd3544eb54 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -70,7 +70,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(timestamp_get());
+	timestamp_init(get_initial_timestamp());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index e3f4686250..d8ed0391e1 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -59,7 +59,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(timestamp_get());
+	timestamp_init(get_initial_timestamp());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 9a8e34b18b..65ff0f8a84 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -125,7 +125,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(timestamp_get());
+	timestamp_init(get_initial_timestamp());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 6252712eba..bb025b0eae 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -14,6 +14,19 @@
  */
 
 #include <arch/io.h>
+#include <cpu/x86/tsc.h>
+
+static void store_initial_timestamp(void)
+{
+	/*
+	 * We have two 32bit scratchpad registers available:
+	 * D0:F0  0xdc (SKPAD)
+	 * D31:F2 0xd0 (SATA SP)
+	 */
+	tsc_t tsc = rdtsc();
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
 
 static void enable_spi_prefetch(void)
 {
@@ -30,5 +43,6 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
+	store_initial_timestamp();
 	enable_spi_prefetch();
 }
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index c40f9b73ea..7c4dafaef6 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -15,8 +15,19 @@
  */
 
 #include <arch/io.h>
+#include <timestamp.h>
+#include <cpu/x86/tsc.h>
 #include "i82801ix.h"
 
+uint64_t get_initial_timestamp(void)
+{
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+	return tsc_to_uint64(base_time);
+}
+
 void i82801ix_early_init(void)
 {
 	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);