- move the XIP_ROM_* flags to src/cpu/x86/Kconfig exclusively

- set them to span the last 64k, instead of the last 128k
  by default
- fixes via CAR for tiny bootblock
- enabled tiny bootblock for via/vt8454c

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/Kconfig

@@ -116,14 +116,6 @@ config CPU_ADDR_BITS
 	int
 	default 36
 
-config XIP_ROM_BASE
-	hex
-	default 0xfffe0000
-
-config XIP_ROM_SIZE
-	hex
-	default 0x20000
-
 config LOGICAL_CPUS
 	bool
 	default y

src/cpu/via/car/cache_as_ram.inc

@@ -139,7 +139,7 @@ clear_fixed_var_mtrr_out:
 	xorl	$0x5c5c5c5c,%eax
 	rep	stosl
 
-	movl	CONFIG_XIP_ROM_BASE, %esi
+	movl	REAL_XIP_ROM_BASE, %esi
 	movl	%esi, %edi
 	movl	$(CONFIG_XIP_ROM_SIZE>>2), %ecx
 	rep	lodsl
@@ -241,10 +241,10 @@ testok:	movb $0x40,%al
 	movl    $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
 	wrmsr        
 	
-	/* cache CONFIG_XIP_ROM_BASE-SIZE to speedup coreboot code */
+	/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
 	movl    $0x206, %ecx
 	xorl    %edx, %edx
-	movl     $CONFIG_XIP_ROM_BASE,%eax
+	movl     $REAL_XIP_ROM_BASE,%eax
 	orl     $(0 | 6), %eax
 	wrmsr
 

src/cpu/x86/Kconfig

@@ -25,8 +25,8 @@ config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 
 config XIP_ROM_BASE
 	hex
-	default 0xfffe0000
+	default 0xffff0000
 
 config XIP_ROM_SIZE
 	hex
-	default 0x20000
+	default 0x10000

src/mainboard/via/vt8454c/Kconfig

@@ -12,6 +12,7 @@ config BOARD_VIA_VT8454C
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
 	select USE_DCACHE_RAM
+	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR
 	string