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soc/intel/common: Provide common block fast_spi_flash_ctrlr 

Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.

Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2017-05-02 19:43:20 -07:00 committed by Martin Roth
parent 35418f9814
commit f1db5fdb4d
4 changed files with 25 additions and 36 deletions
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21
src/soc/intel/apollolake/spi.c
View File

@ -15,28 +15,11 @@
*/
#include <console/console.h>
#include <intelblocks/fast_spi.h>
#include <spi-generic.h>
/* SPI controller managing the fast SPI. */
static int fast_spi_ctrlr_setup(const struct spi_slave *dev)
{
if ((dev->bus != 0) && (dev->cs != 0)) {
printk(BIOS_ERR, "%s: Unsupported device "
"bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs);
return -1;
}
printk(BIOS_INFO, "%s: Found controller for device "
"(bus=0x%x,cs=0x%x)!!\n", __func__, dev->bus, dev->cs);
return 0;
}
static const struct spi_ctrlr fast_spi_ctrlr = {
.setup = fast_spi_ctrlr_setup,
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{ .ctrlr = &fast_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

15
src/soc/intel/common/block/fast_spi/fast_spi_flash.c
View File

@ -350,3 +350,18 @@ int fast_spi_flash_read_wpsr(u8 *sr)
return 0;
}
static int fast_spi_flash_ctrlr_setup(const struct spi_slave *dev)
{
if (dev->cs != 0) {
printk(BIOS_ERR, "%s: Invalid CS for fast SPI bus=0x%x,cs=0x%x!\n",
__func__, dev->bus, dev->cs);
return -1;
}
return 0;
}
const struct spi_ctrlr fast_spi_flash_ctrlr = {
.setup = fast_spi_flash_ctrlr_setup,
};

6
src/soc/intel/common/block/include/intelblocks/fast_spi.h
View File

@ -64,4 +64,10 @@ size_t fast_spi_get_bios_region(size_t *bios_size);
*/
void fast_spi_early_init(uintptr_t spi_base_address);
/*
* Fast SPI flash controller structure to allow SoCs to define bus-controller
* mapping.
*/
extern const struct spi_ctrlr fast_spi_flash_ctrlr;
#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */

19
src/soc/intel/skylake/spi.c
View File

@ -20,28 +20,13 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/spi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <soc/ramstage.h>
#include <spi-generic.h>
/* SPI controller managing the flash-device SPI. */
static int flash_spi_ctrlr_setup(const struct spi_slave *dev)
{
if ((dev->bus != 0) || (dev->cs != 0)) {
printk(BIOS_ERR, "%s: Unsupported device bus=0x%x,cs=0x%x!\n",
__func__, dev->bus, dev->cs);
return -1;
}
return 0;
}
static const struct spi_ctrlr flash_spi_ctrlr = {
.setup = flash_spi_ctrlr_setup,
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{ .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
#if !ENV_SMM
{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
.bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},