soc/intel/quark: use common Intel ACPI hardware definitions

Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:27:12 -05:00
parent bf168e740f
commit f1e22d5c39
2 changed files with 3 additions and 7 deletions

View File

@ -18,11 +18,7 @@
#define _SOC_PM_H_ #define _SOC_PM_H_
#include <stdint.h> #include <stdint.h>
#include <arch/acpi.h>
/* Generic sleep state types */
#define SLEEP_STATE_S0 0
#define SLEEP_STATE_S3 3
#define SLEEP_STATE_S5 5
struct chipset_power_state { struct chipset_power_state {
uint32_t prev_sleep_state; uint32_t prev_sleep_state;

View File

@ -117,7 +117,7 @@ struct chipset_power_state *fill_power_state(void)
{ {
struct chipset_power_state *ps = car_get_var_ptr(&power_state); struct chipset_power_state *ps = car_get_var_ptr(&power_state);
ps->prev_sleep_state = 0; ps->prev_sleep_state = ACPI_S0;
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
return ps; return ps;
} }
@ -147,7 +147,7 @@ void soc_memory_init_params(struct romstage_params *params,
hexdump((void *)0x000ffff0, 0x10); hexdump((void *)0x000ffff0, 0x10);
/* Clear SMI and wake events */ /* Clear SMI and wake events */
if (ps->prev_sleep_state != 3) { if (ps->prev_sleep_state != ACPI_S3) {
printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events);
} }