mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC

Taeko will use two PCIE port signals with one slot, one CLK and one
CLKREQ at next build. In order to accommodate this, probe statements
are added to the devicetree. This only affects NVME SSD and EMMC.

BUG=b:211914322
TEST=Build FSP with debug output enabled, and observe the correct root
ports being initialized depending on the FW_CONFIG values for BOOT_EMMC
and BOOT_NVME.

Cq-Depend: chromium:3358662
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/variants/taeko/overridetree.cb

@@ -241,6 +241,7 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.clk_src = 0,
 			}"
+			probe BOOT_NVME_MASK BOOT_NVME_ENABLED
 		end
 		device ref tbt_pcie_rp0 off end
 		device ref tbt_pcie_rp1 off end
@@ -396,12 +397,21 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp9 on
+			# Enable NVMe PCIE 9 using clk 0
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
-				register "srcclk_pin" = "1"
-				device generic 0 on end
+				register "srcclk_pin" = "0"
+				device generic 0 on
+					probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
+				end
 			end
+			probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
 		end
 		device ref gspi1 on
 			chip drivers/spi/acpi