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soc/intel/alderlake/iomap: Correct the ADL-S reserved range 

Due to incorrectly interpreted DOC #630603, the reserved range
remains the same for all ADL platforms and is sync with
src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the
range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was
only mean for static allocations, but the rest is also reserved. The
only difference between ADL-S and other ADL platforms is Trace Hub
base.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Michał Żygowski 2022-04-28 13:17:56 +02:00
parent 499b7521d5
commit f1f31a38dc
1 changed files with 3 additions and 6 deletions
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9
src/soc/intel/alderlake/include/soc/iomap.h
View File

@ -13,19 +13,16 @@
* Memory-mapped I/O registers.
*/
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#define PCH_PRESERVED_BASE_ADDRESS 0xfe000000
#define PCH_PRESERVED_BASE_SIZE 0x00800000
#define PCH_TRACE_HUB_BASE_ADDRESS 0xfd800000
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
#else
#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
#define PCH_PRESERVED_BASE_SIZE 0x02000000
#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
#endif
#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
#define PCH_PRESERVED_BASE_SIZE 0x02000000
#define UART_BASE_SIZE 0x1000
#define UART_BASE_0_ADDRESS 0xfe03e000