ec/google/chromeec: Update google_chromeec_usb_pd_control()

Add parameter `active_cable` to obtain the cable type
(active or passive) which is needed for USB-C configuration for
some SoCs (at least Intel TGL and ADL), change the function name to
google_chromeec_usb_pd_get_info() for better understanding.

BUG=b:192947843

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Derek Huang 2021-09-29 16:39:01 +08:00 committed by Tim Wawrzynczak
parent 89d8260e3f
commit f1f9b3d5f5
2 changed files with 5 additions and 3 deletions

View File

@ -1477,7 +1477,8 @@ int google_ec_running_ro(void)
return (google_chromeec_get_current_image() == EC_IMAGE_RO);
}
int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode)
int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc,
bool *active_cable, uint8_t *dp_mode)
{
struct ec_params_usb_pd_control pd_control = {
.port = port,
@ -1501,6 +1502,7 @@ int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *
*ufp = (resp.cc_state == PD_CC_DFP_ATTACHED);
*dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC);
*active_cable = !!(resp.control_flags & USB_PD_CTRL_ACTIVE_CABLE);
*dp_mode = resp.dp_mode;
return 0;

View File

@ -34,8 +34,8 @@ int google_chromeec_pd_get_amode(uint16_t svid);
*/
int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags);
/* Returns data role and type of device connected */
int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc,
uint8_t *dp_mode);
int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc,
bool *active_cable, uint8_t *dp_mode);
int google_chromeec_wait_for_displayport(long timeout);
/* Device events */