Various cosmetic fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2007-05-15 07:11:09 +00:00
parent c161808985
commit f1ff2c38d2
6 changed files with 29 additions and 43 deletions

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@ -157,8 +157,8 @@ chip northbridge/amd/gx1
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 0x01 # int 1 for PS/2 keyboard
irq 0x72 = 0x0c # int 12 for PS/2 mouse
irq 0x70 = 0x01 # Int 1 for PS/2 keyboard
irq 0x72 = 0x0c # Int 12 for PS/2 mouse
end
device pnp 2e.6 on # IR
io 0x60 = 0x2e8

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@ -38,33 +38,17 @@
static void main(unsigned long bist)
{
/* Initialize the serial console. */
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
/* Initialize RAM. */
sdram_init();
/* Check all of memory */
#if 0
ram_check(0x00000000, msr.lo);
#endif
#if 0
static const struct {
unsigned long lo, hi;
} check_addrs[] = {
/* Check 16MB of memory @ 0*/
{ 0x00000000, 0x01000000 },
#if TOTAL_CPUS > 1
/* Check 16MB of memory @ 2GB */
{ 0x80000000, 0x81000000 },
#endif
};
int i;
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
/* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}

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@ -71,4 +71,3 @@ checksums
checksum 392 1007 1008

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@ -19,6 +19,7 @@
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>

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@ -39,15 +39,19 @@
* - the additional PCI slot must share the IRQ with the internal USB
*/
#define IRQ_BITMAP_LINK0 0x0200 /* bit 9 means IRQ 9 available for this cs5530 INT input*/
#define IRQ_BITMAP_LINK1 0x0020 /* bit 5 means IRQ 5 available for this cs5530 INT input*/
#define IRQ_BITMAP_LINK2 0x0400 /* bit 10 means IRQ10 available for this cs5530 INT input*/
#define IRQ_BITMAP_LINK3 0x0800 /* bit 11 means IRQ11 available for this cs5530 INT input*/
/* Bit 9 means IRQ 9 is available for this cs5530 INT input. */
#define IRQ_BITMAP_LINK0 0x0200
/* Bit 5 means IRQ 5 is available for this cs5530 INT input. */
#define IRQ_BITMAP_LINK1 0x0020
/* Bit 10 means IRQ10 is available for this cs5530 INT input. */
#define IRQ_BITMAP_LINK2 0x0400
/* Bit 11 means IRQ11 is available for this cs5530 INT input. */
#define IRQ_BITMAP_LINK3 0x0800
const struct irq_routing_table intel_irq_routing_table = {
.signature = PIRQ_SIGNATURE, /* u32 signature */
.version = PIRQ_VERSION, /* u16 version */
.size = 32+16*IRQ_SLOT_COUNT, /* there can be total 4 devices on the bus */
.size = 32+16*IRQ_SLOT_COUNT, /* There can be total 4 devices on the bus */
.rtr_bus = 0x00, /* Where the interrupt router lies (bus) */
.rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
.exclusive_irqs = 0x4C20, /* IRQs devoted exclusively to PCI usage */
@ -88,7 +92,7 @@ const struct irq_routing_table intel_irq_routing_table = {
* the network device is soldered...
*
* Configuration is ommited on purpose in the attempt of solving the
* issue with IRQ panics (this is device is actually eth1)
* issue with IRQ panics (this is device is actually eth1).
[1] = {
.bus = 0x00,
@ -143,7 +147,7 @@ const struct irq_routing_table intel_irq_routing_table = {
.slot = 0x1, /* soldered */
},
/*
* This is a free PCI slot
* This is a free PCI slot.
*/
[3] = {
.bus = 0x00,
@ -208,4 +212,3 @@ unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}

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@ -29,4 +29,3 @@
struct chip_operations mainboard_iei_nova4899r_ops = {
CHIP_NAME("IEI NOVA-4899R Mainboard")
};