Various cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -157,8 +157,8 @@ chip northbridge/amd/gx1
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 0x01 # int 1 for PS/2 keyboard
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irq 0x72 = 0x0c # int 12 for PS/2 mouse
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irq 0x70 = 0x01 # Int 1 for PS/2 keyboard
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irq 0x72 = 0x0c # Int 12 for PS/2 mouse
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end
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device pnp 2e.6 on # IR
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io 0x60 = 0x2e8
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@ -38,33 +38,17 @@
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static void main(unsigned long bist)
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{
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/* Initialize the serial console. */
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w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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/* Halt if there was a built in self test failure. */
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report_bist_failure(bist);
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/* Initialize RAM. */
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sdram_init();
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/* Check all of memory */
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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/* Check RAM. */
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/* ram_check(0x00000000, 640 * 1024); */
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}
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@ -71,4 +71,3 @@ checksums
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checksum 392 1007 1008
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@ -19,6 +19,7 @@
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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@ -39,15 +39,19 @@
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* - the additional PCI slot must share the IRQ with the internal USB
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*/
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#define IRQ_BITMAP_LINK0 0x0200 /* bit 9 means IRQ 9 available for this cs5530 INT input*/
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#define IRQ_BITMAP_LINK1 0x0020 /* bit 5 means IRQ 5 available for this cs5530 INT input*/
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#define IRQ_BITMAP_LINK2 0x0400 /* bit 10 means IRQ10 available for this cs5530 INT input*/
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#define IRQ_BITMAP_LINK3 0x0800 /* bit 11 means IRQ11 available for this cs5530 INT input*/
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/* Bit 9 means IRQ 9 is available for this cs5530 INT input. */
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#define IRQ_BITMAP_LINK0 0x0200
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/* Bit 5 means IRQ 5 is available for this cs5530 INT input. */
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#define IRQ_BITMAP_LINK1 0x0020
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/* Bit 10 means IRQ10 is available for this cs5530 INT input. */
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#define IRQ_BITMAP_LINK2 0x0400
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/* Bit 11 means IRQ11 is available for this cs5530 INT input. */
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#define IRQ_BITMAP_LINK3 0x0800
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const struct irq_routing_table intel_irq_routing_table = {
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.signature = PIRQ_SIGNATURE, /* u32 signature */
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.version = PIRQ_VERSION, /* u16 version */
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.size = 32+16*IRQ_SLOT_COUNT, /* there can be total 4 devices on the bus */
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.size = 32+16*IRQ_SLOT_COUNT, /* There can be total 4 devices on the bus */
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.rtr_bus = 0x00, /* Where the interrupt router lies (bus) */
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.rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
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.exclusive_irqs = 0x4C20, /* IRQs devoted exclusively to PCI usage */
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@ -88,7 +92,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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* the network device is soldered...
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*
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* Configuration is ommited on purpose in the attempt of solving the
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* issue with IRQ panics (this is device is actually eth1)
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* issue with IRQ panics (this is device is actually eth1).
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[1] = {
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.bus = 0x00,
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@ -143,7 +147,7 @@ const struct irq_routing_table intel_irq_routing_table = {
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.slot = 0x1, /* soldered */
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},
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/*
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* This is a free PCI slot
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* This is a free PCI slot.
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*/
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[3] = {
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.bus = 0x00,
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@ -208,4 +212,3 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -29,4 +29,3 @@
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struct chip_operations mainboard_iei_nova4899r_ops = {
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CHIP_NAME("IEI NOVA-4899R Mainboard")
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};
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