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mb/google/hatch: Fix SD card is detected as read only issue 

This patch configures GPIO pin GPP_G7 as NF1 with internal pull down.

As per schematics SD host controller SD_WP pin is not connected to
uSD card connector. Configured gpio pin as NF1 with internal pull down
in order to overcome gpio default state in hatch which makes SoC
SD_WP pin is enable.

BUG=b:137729527
BRANCH=None
TEST=Able to write/read data to/from sd card after mounting card device.

Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-07-18 08:24:12 +05:30
parent 368ade72ea
commit f208f4a123
1 changed files with 6 additions and 2 deletions
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8
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -324,8 +324,12 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
/* G6 : SD_CLK */
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
/* G7 : SD_WP => NC */
PAD_NC(GPP_G7, NONE),
/* G7 : SD_WP
* As per schematics SD host controller SD_WP pin is not connected to
* uSD card connector. In order to overcome gpio default state, ensures
* to configure gpio pin as NF1 with internal 20K pull down.
*/
PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
/*
* H0 : HP_INT_L
*/