soc/intel: Standardize names of common MSRs
Use defined name in Intel 64 and IA-32 Architectures Software Developer’s Manual. Renamed MSRs are (register address, register name): 0x35 MSR_CORE_THREAD_COUNT 0x121 MSR_EMULATE_PM_TIMER 0x1f4 MSR_PRMRR_PHYS_BASE 0x1f5 MSR_PRMRR_PHYS_MASK 0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE 0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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@ -210,7 +210,7 @@ void enable_pm_timer_emulation(void)
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msr.hi = (3579545ULL << 32) / CTC_FREQ;
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/* Set PM1 timer IO port and enable */
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msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
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wrmsr(MSR_EMULATE_PM_TMR, msr);
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wrmsr(MSR_EMULATE_PM_TIMER, msr);
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}
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static int rtc_failed(uint32_t gen_pmcon1)
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@ -622,7 +622,7 @@ static int get_cpu_count(void)
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int num_threads;
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int num_cores;
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msr = rdmsr(CORE_THREAD_COUNT_MSR);
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msr = rdmsr(MSR_CORE_THREAD_COUNT);
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num_threads = (msr.lo >> 0) & 0xffff;
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num_cores = (msr.lo >> 16) & 0xffff;
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printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
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@ -17,7 +17,7 @@
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#define _BROADWELL_MSR_H_
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define CORE_THREAD_COUNT_MSR 0x35
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#define MSR_CORE_THREAD_COUNT 0x35
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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@ -33,12 +33,12 @@
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define EMRRphysBase_MSR 0x1f4
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#define EMRRphysMask_MSR 0x1f5
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#define MSR_PRMRR_PHYS_BASE 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define MSR_POWER_CTL 0x1fc
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define UNCORE_EMRRphysBase_MSR 0x2f4
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#define UNCORE_EMRRphysMask_MSR 0x2f5
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
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#define SMM_FEATURE_CONTROL_MSR 0x4e0
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#define SMM_CPU_SAVE_EN (1 << 1)
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@ -45,8 +45,8 @@ static inline void write_emrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
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wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);
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wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->emrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->emrr_mask);
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}
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static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
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@ -55,8 +55,8 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
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"Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_emrr_base.lo,
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relo_params->uncore_emrr_mask.lo);
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wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);
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wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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@ -185,7 +185,7 @@ static void enable_pm_timer_emulation(void)
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/* Set PM1 timer IO port and enable*/
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msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
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EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
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wrmsr(MSR_EMULATE_PM_TMR, msr);
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wrmsr(MSR_EMULATE_PM_TIMER, msr);
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}
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/* All CPUs including BSP will run the following function. */
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@ -33,7 +33,7 @@
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#define MSR_POWER_MISC 0x120
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#define ENABLE_IA_UNTRUSTED (1 << 6)
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#define FLUSH_DL1_L2 (1 << 8)
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#define MSR_EMULATE_PM_TMR 0x121
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#define MSR_EMULATE_PM_TIMER 0x121
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#define EMULATE_DELAY_OFFSET_VALUE 20
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#define EMULATE_PM_TMR_EN (1 << 16)
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#define EMULATE_DELAY_VALUE 0x13
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@ -60,8 +60,8 @@
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#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7)
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#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12)
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define PRMRR_PHYS_BASE_MSR 0x1f4
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#define PRMRR_PHYS_MASK_MSR 0x1f5
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#define MSR_PRMRR_PHYS_BASE 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define PRMRR_PHYS_MASK_LOCK (1 << 10)
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#define PRMRR_PHYS_MASK_VALID (1 << 11)
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#define MSR_POWER_CTL 0x1fc
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@ -83,7 +83,7 @@ void prmrr_core_configure(void)
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if (!soc_sgx_enabled() || !is_sgx_supported())
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return;
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msr = rdmsr(PRMRR_PHYS_MASK_MSR);
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msr = rdmsr(MSR_PRMRR_PHYS_MASK);
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/* If it is locked don't attempt to write PRMRR MSRs. */
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if (msr.lo & PRMRR_PHYS_MASK_LOCK)
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return;
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@ -109,19 +109,19 @@ void prmrr_core_configure(void)
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* - Clear the valid bit in PRMRR mask MSR
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* - Lock PRMRR MASK MSR */
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prmrr_base.data32.lo |= MTRR_TYPE_WRBACK;
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wrmsr(PRMRR_PHYS_BASE_MSR, (msr_t) {.lo = prmrr_base.data32.lo,
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wrmsr(MSR_PRMRR_PHYS_BASE, (msr_t) {.lo = prmrr_base.data32.lo,
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.hi = prmrr_base.data32.hi});
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prmrr_mask.data32.lo &= ~PRMRR_PHYS_MASK_VALID;
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prmrr_mask.data32.lo |= PRMRR_PHYS_MASK_LOCK;
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wrmsr(PRMRR_PHYS_MASK_MSR, (msr_t) {.lo = prmrr_mask.data32.lo,
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wrmsr(MSR_PRMRR_PHYS_MASK, (msr_t) {.lo = prmrr_mask.data32.lo,
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.hi = prmrr_mask.data32.hi});
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}
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static int is_prmrr_set(void)
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{
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msr_t prmrr_base, prmrr_mask;
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prmrr_base = rdmsr(PRMRR_PHYS_BASE_MSR);
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prmrr_mask = rdmsr(PRMRR_PHYS_MASK_MSR);
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prmrr_base = rdmsr(MSR_PRMRR_PHYS_BASE);
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prmrr_mask = rdmsr(MSR_PRMRR_PHYS_MASK);
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/* If PRMRR base is zero and PRMRR mask is locked
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* then PRMRR is not set */
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@ -191,7 +191,7 @@ static void activate_sgx(void)
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static int is_prmrr_approved(void)
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{
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msr_t msr;
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msr = rdmsr(PRMRR_PHYS_MASK_MSR);
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msr = rdmsr(MSR_PRMRR_PHYS_MASK);
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if (msr.lo & PRMRR_PHYS_MASK_VALID) {
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printk(BIOS_INFO, "SGX: MCHECK approved SGX PRMRR\n");
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return 1;
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@ -19,7 +19,7 @@
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#define _DENVERTON_NS_MSR_H_
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define CORE_THREAD_COUNT_MSR 0x35
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#define MSR_CORE_THREAD_COUNT 0x35
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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@ -36,11 +36,11 @@
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define EMRR_PHYS_BASE_MSR 0x1f4
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#define EMRR_PHYS_MASK_MSR 0x1f5
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define MSR_POWER_CTL 0x1fc
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4
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#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
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#define SMM_FEATURE_CONTROL_MSR 0x4e0
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#define SMM_CPU_SAVE_EN (1 << 1)
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@ -35,7 +35,7 @@
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/* MTRR_CAP_MSR bits */
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#define SMRR_SUPPORTED (1 << 11)
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#define PRMRR_SUPPORTED (1 << 12)
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#define PRMRRphysBase_MSR 0x1f4
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#define PRMRRphysMask_MSR 0x1f5
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#define MSR_PRMRR_PHYS_BASE 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#endif /* _SOC_MSR_H_ */
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@ -46,8 +46,8 @@ static inline void write_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
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wrmsr(PRMRRphysBase_MSR, relo_params->prmrr_base);
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wrmsr(PRMRRphysMask_MSR, relo_params->prmrr_mask);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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@ -420,7 +420,7 @@ static void enable_pm_timer_emulation(void)
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/* Set PM1 timer IO port and enable*/
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msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
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EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
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wrmsr(MSR_EMULATE_PM_TMR, msr);
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wrmsr(MSR_EMULATE_PM_TIMER, msr);
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}
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/* All CPUs including BSP will run the following function. */
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@ -528,7 +528,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
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* be reloaded after the core PRMRR MSRs are programmed.
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*/
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msr1 = rdmsr(MTRR_CAP_MSR);
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msr2 = rdmsr(PRMRR_PHYS_BASE_MSR);
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msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);
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if (msr2.lo && (current_patch_id == new_patch_id - 1))
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return 0;
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else
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