soc/intel/broadwell/pch: Drop `acpi_sci_irq` function

The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using
common MADT code on Broadwell, hardcode it as 9 everywhere.

Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-11-23 12:40:07 +01:00 committed by Patrick Georgi
parent e0f058ffa8
commit f21e5c06cd
4 changed files with 2 additions and 33 deletions

View File

@ -139,9 +139,6 @@ void disable_all_gpe(void);
void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
/* Return the selected ACPI SCI IRQ */
int acpi_sci_irq(void);
/* STM Support */
uint16_t get_pmbase(void);

View File

@ -21,7 +21,7 @@
unsigned long acpi_fill_madt(unsigned long current)
{
int sci = acpi_sci_irq();
int sci = 9;
acpi_madt_irqoverride_t *irqovr;
uint16_t flags = MP_IRQ_TRIGGER_LEVEL;

View File

@ -10,7 +10,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq();
fadt->sci_int = 9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;

View File

@ -412,34 +412,6 @@ void disable_gpe(u32 mask)
outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD));
}
int acpi_sci_irq(void)
{
int scis = pci_read_config32(PCH_DEV_LPC, ACPI_CNTL) & SCI_IRQ_SEL;
int sci_irq = 9;
/* Determine how SCI is routed. */
switch (scis) {
case SCIS_IRQ9:
case SCIS_IRQ10:
case SCIS_IRQ11:
sci_irq = scis - SCIS_IRQ9 + 9;
break;
case SCIS_IRQ20:
case SCIS_IRQ21:
case SCIS_IRQ22:
case SCIS_IRQ23:
sci_irq = scis - SCIS_IRQ20 + 20;
break;
default:
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
sci_irq = 9;
break;
}
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
return sci_irq;
}
int platform_is_resuming(void)
{
if (!(inw(get_pmbase() + PM1_STS) & WAK_STS))