soc/intel/broadwell/pch: Drop `acpi_sci_irq` function
The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using common MADT code on Broadwell, hardcode it as 9 everywhere. Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -139,9 +139,6 @@ void disable_all_gpe(void);
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void enable_gpe(uint32_t mask);
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void disable_gpe(uint32_t mask);
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/* Return the selected ACPI SCI IRQ */
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int acpi_sci_irq(void);
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/* STM Support */
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uint16_t get_pmbase(void);
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@ -21,7 +21,7 @@
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unsigned long acpi_fill_madt(unsigned long current)
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{
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int sci = acpi_sci_irq();
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int sci = 9;
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acpi_madt_irqoverride_t *irqovr;
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uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
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@ -10,7 +10,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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const uint16_t pmbase = ACPI_BASE_ADDRESS;
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fadt->sci_int = acpi_sci_irq();
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fadt->sci_int = 9;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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@ -412,34 +412,6 @@ void disable_gpe(u32 mask)
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outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD));
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}
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int acpi_sci_irq(void)
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{
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int scis = pci_read_config32(PCH_DEV_LPC, ACPI_CNTL) & SCI_IRQ_SEL;
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int sci_irq = 9;
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/* Determine how SCI is routed. */
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switch (scis) {
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case SCIS_IRQ9:
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case SCIS_IRQ10:
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case SCIS_IRQ11:
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sci_irq = scis - SCIS_IRQ9 + 9;
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break;
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case SCIS_IRQ20:
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case SCIS_IRQ21:
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case SCIS_IRQ22:
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case SCIS_IRQ23:
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sci_irq = scis - SCIS_IRQ20 + 20;
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break;
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default:
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printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
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sci_irq = 9;
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break;
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}
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printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
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return sci_irq;
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}
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int platform_is_resuming(void)
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{
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if (!(inw(get_pmbase() + PM1_STS) & WAK_STS))
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