intel/fsp_baytrail: Support Baytrail FSP Gold4 release
Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION structure to include these new PCD options and initialized the setting when given in devicetree.cb. Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/10838 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2014 Intel Corporation
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* Copyright (C) 2014-2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -189,6 +189,38 @@ struct soc_intel_fsp_baytrail_config {
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#define TXE_UMA_DISABLE UPD_DISABLE
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#define TXE_UMA_ENABLE UPD_ENABLE
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/*
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* PcdOsSelection
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* Selection 0x1 , "Android"
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* Selection 0x4 , "Linux OS"
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*/
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uint8_t PcdOsSelection;
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#define OS_SELECTION_DEFAULT UPD_DEFAULT
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#define OS_SELECTION_ANDROID INCREMENT_FOR_DEFAULT(1)
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#define OS_SELECTION_LINUX INCREMENT_FOR_DEFAULT(4)
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/* PcdEMMC45DDR50Enabled */
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uint8_t PcdEMMC45DDR50Enabled;
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#define EMMC45_DDR50_DEFAULT UPD_DEFAULT
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#define EMMC45_DDR50_DISABLE UPD_DISABLE
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#define EMMC45_DDR50_ENABLE UPD_ENABLE
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/* PcdEMMC45HS200Enabled */
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uint8_t PcdEMMC45HS200Enabled;
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#define EMMC45_HS200_DEFAULT UPD_DEFAULT
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#define EMMC45_HS200_DISABLE UPD_DISABLE
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#define EMMC45_HS200_ENABLE UPD_ENABLE
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/* PcdEMMC45RetuneTimerValue */
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uint8_t PcdEMMC45RetuneTimerValue;
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#define EMMC45_RETURN_TIMER_DEFAULT UPD_DEFAULT
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/* PcdEnableIgd */
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uint8_t PcdEnableIgd;
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#define ENABLE_IGD_DEFAULT UPD_DEFAULT
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#define ENABLE_IGD_DISABLE UPD_DISABLE
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#define ENABLE_IGD_ENABLE UPD_ENABLE
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/* Memory down data */
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uint8_t EnableMemoryDown;
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#define MEMORY_DOWN_DEFAULT UPD_DEFAULT
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2014 Intel Corporation
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* Copyright (C) 2014-2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -112,6 +112,11 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
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UPD_DEFAULT_CHECK(PcdSccEnablePciMode);
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UPD_DEFAULT_CHECK(IgdRenderStandby);
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UPD_DEFAULT_CHECK(TxeUmaEnable);
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UPD_DEFAULT_CHECK(PcdOsSelection);
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UPD_DEFAULT_CHECK(PcdEMMC45DDR50Enabled);
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UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled);
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UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue);
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UPD_DEFAULT_CHECK(PcdEnableIgd);
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if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) ||
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(config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE))
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@ -97,7 +97,12 @@ typedef struct _UPD_DATA_REGION {
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UINT8 PcdSccEnablePciMode; /* Offset 0x004D */
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UINT8 IgdRenderStandby; /* Offset 0x004E */
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UINT8 TxeUmaEnable; /* Offset 0x004F */
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UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */
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UINT8 PcdOsSelection; /* Offset 0x0050 */
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UINT8 PcdEMMC45DDR50Enabled; /* Offset 0x0051 */
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UINT8 PcdEMMC45HS200Enabled; /* Offset 0x0052 */
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UINT8 PcdEMMC45RetuneTimerValue; /* Offset 0x0053 */
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UINT8 PcdEnableIgd; /* Offset 0x0054 */
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UINT8 UnusedUpdSpace1[155]; /* Offset 0x0055 */
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MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */
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UINT16 PcdRegionTerminator; /* Offset 0x0100 */
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} UPD_DATA_REGION;
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